Data Manual
SM320F2812-HT Contents
SM320F2812-HT
Peripherals
SPI Slave Mode Timing
List of Figures
General-Purpose Input Timing
List of Tables
Interrupt Switching Characteristics
149
Copyright 2009-2010, Texas Instruments Incorporated
Digital Signal Processor
Check for Samples SM320F2812-HT
Supports Extreme Temperature Applications
Introduction
Description
Device Summary
Hardware Features
Feature
F2812
Coordinates Thickness Finish Potential
Die Layout
DIE PAD Backside DIE Size DIE PAD Size
55.0 x 64.0 μm
Pin Assignments
SM320F2812 172-Pin HFG Cqfp Top View
Center Description HFG Xintf Signals
Signal Descriptions
Signal Descriptions1
PIN no DIE PAD
Signal Descriptions
Center Description HFG
Center Description HFG Jtag and Miscellaneous Signals
TMS
Trst
TCK
TDI
Center Description HFG ADC Analog Input Signals
Center Description HFG Power Signals
SM320F2812-HT
Gpiob or EVB Signals
Peripheral PIN no DIE PAD Gpio DIE PAD no
Gpiod or EVB Signals
Signal HFG Center
Gpiod or EVA Signals
Gpioe or Interrupt Signals
Gpiof or McBSP Signals
Signal HFG Center Gpiof or can Signals
Gpiof or XF CPU Output Signal
GPIOG4 Scitxdb O
Signal HFG Center Gpiog or SCI-B Signals
GPIOG5 Scirxdb
Functional Overview
Memory Map
F2812 Memory Map See Notes A. Through G
Addresses of Flash Sectors in F2812
Address Range Program and Data Space
Comments
Wait States
Area
H0 Saram
Memory Bus Harvard Bus Architecture
Brief Descriptions
1 C28x CPU
Peripheral Bus
Flash
Boot ROM
External Interface Xintf
7 L0, L1, H0 SARAMs
Security
Boot Mode Selection
Boot Mode Selected GPIOF4 GPIOF12 GPIOF3 GPIOF2
Code Security Module Disclaimer
External Interrupts XINT1, XINT2, XINT13, Xnmi
Low-Power Modes
Peripheral Interrupt Expansion PIE Block
Oscillator and PLL
General-Purpose Input/Output Gpio Multiplexer
18 32-Bit CPU Timers 0, 1
Peripheral Frames 0, 1, 2 PFn
Control Peripherals
Serial Port Peripherals
Register Map
Peripheral Frame 1 Registers1
Access Type
Peripheral Frame 0 Registers1
Name Address Range
Peripheral Frame 2 Registers1
External Interface, Xintf
Device Emulation Registers
Device Emulation Registers
XZCS6 XZCS6AND7
XZCS0XZCS0AND1 XZCS1
XZCS2
XZCS7 XWE XRD XR/W Xready XMP/MC Xhold Xholda Xclkout
Xrevision Register
Xintf Configuration and Control Register Mappings
Timing Registers
Xrevision Register Bit Definitions
Interrupts
Intm
INT1 INT2 INT11 INT12
CPU PIE Interrupts
11. PIE Configuration and Control Registers1
External Interrupts
12. External Interrupts Registers
Clock and Reset Domains
System Control
13. PLL, Clocking, Watchdog, and Low-Power Mode Registers1
OSC and PLL Block
14. Pllcr Register Bit Definitions
PLL-Based Clock Module
PLL Mode Remarks Sysclkout
Loss of Input Clock
External Reference Oscillator Clock Option
Watchdog Block
Mode
Low-Power Modes Block
16. F2812 Low-Power Modes
Oscclk Clkin Sysclkout
Prdhprd
32-Bit CPU-Timers 0/1/2
Tddrhtddr
Pschpsc TCR.4
INT1 to INT12 C28x
INT13 PIE TINT1 TINT0 CPU-TIMER
INT14 XINT13 TINT2
CPU-Timers 0, 1, 2 Configuration and Control Registers
Event Manager Modules EVA EVB Signal
Module and Signal Names for EVA and EVB
Event Manager Modules EVA, EVB
EVA Registers1
Event Manager a Functional Block Diagram See Note a
Full-Compare Units
General-Purpose GP Timers
Double Update PWM Mode
Programmable Deadband Generator
Quadrature-Encoder Pulse QEP Circuit
PWM Characteristics
Capture Unit
External ADC Start-of-Conversion
Enhanced Analog-to-Digital Converter ADC Module
ADCINA7
Adcenclk Hspclk
MUX ADCINA0
ADC
Adclo
ADCINA70
ADCINB70
Adcbgrefin ²
Adclo Adcbgrefin
SM320F2812-HT
Avddrefbg Avssrefbg
ADC Registers1
Enhanced Controller Area Network eCAN Module
SN65HVD23x
Unit
Can Bus
ECAN Memory Map
Can Registers Map1
Register Name Address
Where Clksrg source could be LSPCLK, CLKX, or CLKR.2
Multichannel Buffered Serial Port McBSP Module
FSX
TX Fifo
Lspclk
Clkx
HEX
Name Address Type Reset Value Description
McBSP Register Summary
Data REGISTERS, RECEIVE, Transmit
Fifo Mode Registers applicable only in Fifo mode
Serial Communications Interface SCI Module
SCI-A Registers1
SCI-B Registers1
10. Serial Communications Interface SCI Module Block Diagram
−−−−−
Serial Peripheral Interface SPI Module
10. SPI Registers1
−−−−−
−−−−−
11. Gpio Mux Registers1 2
Register Description
12. Gpio Data Registers1
PIN
Software Development Tools
Device and Development Support Tool Nomenclature
Hardware Development Tools
Documentation Support
SM320F2812-HT
Absolute Maximum Ratings
Value Unit
MIN NOM MAX Unit
Electrical Characteristics
Recommended Operating Conditions
Parameter Test Conditions MIN TYP MAX Unit
Die Junction Temperature C
Hours
Mode Test Conditions
Current Consumption Graphs
Vddaio
Peripheral Module
Power Sequencing Requirements
Reducing Current Consumption
DD Current Reduction mA
Recommended Low-Dropout Regulators
Signal Transition Levels
Supplier Part Number
VOH 80% 20% VOL
Timing Parameter Symbology
VIH 90% 10% VIL
Test Load Circuit
General Notes on Timing Parameters
85 pF
Input Clock Requirements
Clock Requirements and Characteristics
Device Clock Table
Clock Table and Nomenclature
Xclkin Timing Requirements PLL Disabled1
Output Clock Characteristics
Xclkin Timing Requirements PLL Bypassed or Enabled
Possible PLL Configuration Modes1
Reset Timing
Reset XRS Timing Requirements1
XF/XPLLDIS
GPIOF14
Xclkout XRS
XF/XPLLDIS XMP/MC
GPIOF14/XF
Xclkin Xclkout XRS
XCLKIN/8
XCLKIN/2
A0−A15
Low-Power Mode Wakeup Timing
10. Idle Mode Switching Characteristics1
Xclkout = Sysclkout
11. Standby Mode Switching Characteristics1
XCLKOUT²
Device Status Flushing Pipeline Wake−up Signal
Standby
Sysclkout Cycles
12. Halt Mode Switching Characteristics1
Event Manager Interface
PWM Timing
Parameter Test Conditions MIN
13. PWM Switching Characteristics1
14. Timer and Capture Unit Timing Requirements1
MAX Unit
17. Interrupt Switching Characteristics
Interrupt Timing
18. Interrupt Timing Requirements
19. General-Purpose Output Switching Characteristics
General-Purpose Input/Output Gpio Output Timing
TxCTRIP, CxTRIP PDPINTx See Note B
Qualprd Sysclkout
General-Purpose Input/Output Gpio Input Timing
Qualprd = 1 2 x Sysclkout cycles x Output From Qualifier
21. SPI Master Mode External Timing Clock Phase = 01 2
SPI Master Mode Timing
GPIOxn
Spisimo
Spisomi Master In Data Must Be Valid
22. SPI Master Mode External Timing Clock Phase = 11 2
Data Valid
Spisomi
SPI Slave Mode Timing
23. SPI Slave Mode External Timing Clock Phase = 01 2
SM320F2812-HT
24. SPI Slave Mode External Timing Clock Phase = 11 2
Spisimo Data Must Be Valid
SM320F2812-HT
27. Valid and Invalid Timing1
26. Xtiming Register Configuration Restrictions1
External Interface Xintf Timing
X2TIMING =
29. Valid and Invalid Timing when using Synchronous XREADY1
28. Xtiming Register Configuration Restrictions1
30. Xtiming Register Configuration Restrictions1
Mode Sysclkout Xtimclk Xclkout
31. Xtiming Register Configuration Restrictions1
33. Xintf Clock Configurations
32. Asynchronous XREADY1
28. Relationship Between Xtimclk and Sysclkout
XINTCNF2 Clkoff Xtimclk Clkmode
Xintf Signal Alignment to Xclkout
XR/W
XCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk
External Interface Read Timing
35. External Memory Interface Read Timing Requirements1
XZCS0AND1, XZCS2 XZCS6AND7
XCLKOUT=XTIMCLK
External Interface Write Timing
Lead Active
Dout
SM320F2812-HT
Setup time, Xready Synch low before Xclkout high/low
DIN
WS Synch Active Lead Trail
XREADYSynch
XCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk XZCS0AND1, XZCS2
WS Asynch
XREADYAsynch
Parameter MIN MAX Unit
33. Write With Synchronous Xready Access
34. Write With Asynchronous Xready Access
Xhold and Xholda
XWE, XRD XZCS6AND7 XR/W
XR/W XZCS0AND1
XHOLD/XHOLDA Timing
44. XHOLD/XHOLDA Timing Requirements Xclkout = XTIMCLK1 2
XZCS2 XZCS6AND7
XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 Xtimclk
36. XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 Xtimclk
On-Chip Analog-to-Digital Converter
ADC Absolute Maximum Ratings
46. DC Specifications1
MIN TYP MAX
47. AC Specifications1
48. Current Consumption1
TYP ADC Operating MODE/CONDITIONS
Pwdnbg Pwdnref
ADC Power-Up Control Bit Timing
ADCIN0
Pwdnadc
Sequential Sampling Mode Single Channel Smode =
Detailed Description
Sample n +
50. Sequential Sampling Mode Timing1
Clock Remarks
Simultaneous Sampling Mode Dual-Channel Smode =
AT 25-MHz ADC
Definitions of Specifications and Terminology
52. McBSP Timing Requirements1 2
Multichannel Buffered Serial Port McBSP Timing
McBSP Transmit and Receive Timing
Clkg + Clksrg
53. McBSP Switching Characteristics1 2
Dxena =
M1, M11 M2, M12 M13
M16 M18
M17 M18
M19
Master Slave Unit MIN MAX
McBSP as SPI Master or Slave Timing
Parameter Master Slave Unit MIN MAX
M39
M49
M58
Recommended Operating Conditions
63. Flash/OTP Access Timing1
Flash Timing
62. Flash Parameters at 150-MHz SYSCLKOUT1
WAIT-STATE Random Wait STATE2
64. Minimum Required Wait-States at Different Frequencies
250
Mechanical Data
Orderable Device
Package Type Pins Package Qty Eco Plan Lead
Samples
Page
DSP
Products Applications
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