Texas Instruments SM320F2812-HT Center Description HFG Jtag and Miscellaneous Signals

SM320F2812-HT

www.ti.com

SGUS062A –JUNE 2009 –REVISED APRIL 2010

Table 2-3. Signal Descriptions (1)

(continued)

PIN NO.

DIE PAD

DIE PAD

DIE PAD

I/O/Z (2)

PU/PD (3)

NAME

172-PIN

X-CENTER

Y-CENTER

DESCRIPTION

HFG

NO.

(μm)

(μm)

JTAG AND MISCELLANEOUS SIGNALS

Oscillator Input – input to the internal

oscillator. This pin is also used to feed an

external clock. The 28× can be operated

with an external clock source, provided that

the proper voltage levels be driven on the

X1/XCLKIN pin. It should be noted that the

X1/XCLKIN

75

88

5361.5

3668.7

I

X1/XCLKIN pin is referenced to the 1.8-V

(or 1.9-V) core digital power supply (VDD),

rather than the 3.3-V I/O supply (VDDIO). A

clamping diode may be used to clamp a

buffered clock signal to ensure that the

logic-high level does not exceed VDD

(1.8 V or 1.9 V) or a 1.8-V oscillator may be

used.

X2

74

87

5361.5

3582.6

O

Oscillator Output

Output clock derived from SYSCLKOUT to

be used for external wait-state generation

and as a general-purpose clock source.

XCLKOUT is either the same frequency,

XCLKOUT

117

132

1701.2

5057.5

O

–

1/2 the frequency, or 1/4 the frequency of

SYSCLKOUT. At reset, XCLKOUT =

SYSCLKOUT/4. The XCLKOUT signal can

be turned off by setting bit 3 (CLKOFF) of

the XINTCNF2 register to 1.

TESTSEL

131

147

42.6

4764.6

I

PD

Test Pin. Reserved for TI. Must be

connected to ground.

Device Reset (in) and Watchdog Reset

(out).

Device reset.

causes the device to

XRS

terminate execution. The PC points to the

address contained at the location

0x3FFFC0. When

XRS

is brought to a high

level, execution begins at the location

pointed to by the PC. This pin is driven low

XRS

156

175

42.6

2077.8

I/O

PU

by the DSP when a watchdog reset occurs.

During watchdog reset, the XRS pin is

driven low for the watchdog reset duration

of 512 XCLKIN cycles.

The output buffer of this pin is an

open-drain with an internal pullup (100 μA,

typical). It is recommended that this pin be

driven by an open-drain device.

TEST1

66

76

5361.5

2522.3

I/O

–

Test Pin. Reserved for TI. On F281x

devices, TEST1 must be left unconnected.

TEST2

65

75

5361.5

2436.1

I/O

–

Test Pin. Reserved for TI. On F281x

devices, TEST2 must be left unconnected.

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