Texas Instruments SM320F2812-HT Adcenclk Hspclk, MUX ADCINA0, ADCINA7, ADCINB0 ADCINB7, Eva Soc

SM320F2812-HT

www.ti.com SGUS062A –JUNE 2009 –REVISED APRIL 2010

System

Control Block

High-Speed

Prescaler

SYSCLKOUT

C28x

ADCENCLK

HSPCLK

	Analog		Result Registers
	MUX
ADCINA0			Result Reg 0
		S/H	Result Reg 1
ADCINA7
		12-Bit	Result Reg 7
		ADC	Result Reg 8
		Module
ADCINB0
		S/H
ADCINB7			Result Reg 15
		ADC Control Registers
S/W
EVA	SOC	Sequencer 1	Sequencer 2	SOC
ADCSOC

Figure 4-4. Block Diagram of the F2812 ADC Module

70A8h

70AFh

70B0h

70B7h

S/W

EVB

To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins

( VDDA1/VDDA2 , AVDDREFBG) from the digital supply. Figure 4-5shows the ADC pin connections for the F2812 device.

NOTE

1.The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is controlled by the high-speed peripheral clock (HSPCLK).

2.The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:

ADCENCLK: On reset, this signal is low. While reset is active-low (XRS), the clock to the register still functions. This is necessary to make sure all registers and modes go into their default reset state. The analog module is in a low-power inactive state. As soon as reset goes high, then the clock to the registers is disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers is enabled and the analog module is enabled. There is a certain time delay (ms range) before the ADC is stable and can be used.

HALT: This signal only affects the analog module. It does not affect the registers. If low, the ADC module is powered. If high, the ADC module goes into low-power mode. The HALT mode stops the clock to the CPU, which stops the HSPCLK. Therefore the ADC register logic is turned off indirectly.

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