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Texas Instruments SM320F2812-HT Signal HFG Center Gpiog or SCI-B Signals, GPIOG4 Scitxdb O

Models: SM320F2812-HT

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SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010www.ti.com

Signal Descriptions (Continued) (1) (continued)

	PERIPHERAL	PIN NO.		DIE PAD	DIE PAD
GPIO			DIE PAD NO.			I/O/Z (2)	PU/PD (3)	DESCRIPTION
GPIO		172-PIN	DIE PAD NO.			I/O/Z (2)	PU/PD (3)	DESCRIPTION
	SIGNAL	HFG		X-CENTER	Y-CENTER
		HFG

			GPIOG OR SCI-B SIGNALS

								GPIO or SCI
GPIOG4	SCITXDB (O)	88	102	5098.0	5057.5	I/O/Z	–	asynchronous serial
								port transmit data

								GPIO or SCI
GPIOG5	SCIRXDB (I)	89	103	5003.3	5057.5	I/O/Z	–	asynchronous serial
								port receive data

NOTE

Other than the power supply pins, no pin should be driven before the 3.3-V rail has reached recommended operating conditions.

26 IntroductionCopyright © 2009–2010, Texas Instruments Incorporated

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Texas Instruments SM320F2812-HT specifications Signal HFG Center Gpiog or SCI-B Signals, GPIOG4 Scitxdb O, GPIOG5 Scirxdb

Contents

Data Manual SM320F2812-HT Contents SM320F2812-HT PeripheralsSPI Slave Mode Timing List of Figures General-Purpose Input Timing List of Tables Interrupt Switching Characteristics 149 Copyright 2009-2010, Texas Instruments Incorporated Digital Signal Processor Check for Samples SM320F2812-HTSupports Extreme Temperature Applications Introduction DescriptionDevice Summary Hardware FeaturesFeature F2812Coordinates Thickness Finish Potential Die LayoutDIE PAD Backside DIE Size DIE PAD Size 55.0 x 64.0 μmPin Assignments SM320F2812 172-Pin HFG Cqfp Top ViewCenter Description HFG Xintf Signals Signal DescriptionsSignal Descriptions1 PIN no DIE PADSignal Descriptions Center Description HFGCenter Description HFG Jtag and Miscellaneous Signals TMS TrstTCK TDICenter Description HFG ADC Analog Input Signals Center Description HFG Power Signals Peripheral PIN no DIE PAD Gpio DIE PAD no Gpiob or EVB SignalsSM320F2812-HT Gpiod or EVB Signals Signal HFG CenterGpiod or EVA Signals Gpioe or Interrupt SignalsGpiof or XF CPU Output Signal Signal HFG Center Gpiof or can SignalsGpiof or McBSP Signals GPIOG5 Scirxdb Signal HFG Center Gpiog or SCI-B SignalsGPIOG4 Scitxdb O Functional Overview Memory Map F2812 Memory Map See Notes A. Through GAddresses of Flash Sectors in F2812 Address Range Program and Data SpaceComments Wait StatesArea H0 SaramMemory Bus Harvard Bus Architecture Brief Descriptions1 C28x CPU Peripheral BusFlash Boot ROMExternal Interface Xintf 7 L0, L1, H0 SARAMsSecurity Boot Mode SelectionBoot Mode Selected GPIOF4 GPIOF12 GPIOF3 GPIOF2 Code Security Module DisclaimerExternal Interrupts XINT1, XINT2, XINT13, Xnmi Low-Power ModesPeripheral Interrupt Expansion PIE Block Oscillator and PLLGeneral-Purpose Input/Output Gpio Multiplexer 18 32-Bit CPU Timers 0, 1Peripheral Frames 0, 1, 2 PFn Control PeripheralsSerial Port Peripherals Register MapPeripheral Frame 1 Registers1 Access TypePeripheral Frame 0 Registers1 Name Address RangePeripheral Frame 2 Registers1 Device Emulation Registers Device Emulation RegistersExternal Interface, Xintf XZCS6 XZCS6AND7 XZCS0XZCS0AND1 XZCS1XZCS2 XZCS7 XWE XRD XR/W Xready XMP/MC Xhold Xholda XclkoutXrevision Register Xintf Configuration and Control Register MappingsTiming Registers Xrevision Register Bit DefinitionsInterrupts CPU PIE Interrupts INT1 INT2 INT11 INT12Intm 11. PIE Configuration and Control Registers1 External Interrupts 12. External Interrupts RegistersClock and Reset Domains System Control13. PLL, Clocking, Watchdog, and Low-Power Mode Registers1 OSC and PLL Block 14. Pllcr Register Bit DefinitionsPLL-Based Clock Module PLL Mode Remarks SysclkoutLoss of Input Clock External Reference Oscillator Clock OptionWatchdog Block Mode Low-Power Modes Block16. F2812 Low-Power Modes Oscclk Clkin SysclkoutPrdhprd 32-Bit CPU-Timers 0/1/2Tddrhtddr Pschpsc TCR.4INT14 XINT13 TINT2 INT13 PIE TINT1 TINT0 CPU-TIMERINT1 to INT12 C28x CPU-Timers 0, 1, 2 Configuration and Control Registers Event Manager Modules EVA, EVB Module and Signal Names for EVA and EVBEvent Manager Modules EVA EVB Signal EVA Registers1 Event Manager a Functional Block Diagram See Note a Full-Compare Units General-Purpose GP TimersDouble Update PWM Mode Programmable Deadband GeneratorQuadrature-Encoder Pulse QEP Circuit PWM CharacteristicsCapture Unit External ADC Start-of-ConversionEnhanced Analog-to-Digital Converter ADC Module ADCINA7 Adcenclk HspclkMUX ADCINA0 ADCAdclo ADCINA70ADCINB70 Adcbgrefin ²Avddrefbg Avssrefbg SM320F2812-HTAdclo Adcbgrefin ADC Registers1 Enhanced Controller Area Network eCAN Module Can Bus UnitSN65HVD23x ECAN Memory Map Can Registers Map1 Register Name AddressWhere Clksrg source could be LSPCLK, CLKX, or CLKR.2 Multichannel Buffered Serial Port McBSP ModuleFSX TX FifoLspclk ClkxHEX Name Address Type Reset Value DescriptionMcBSP Register Summary Data REGISTERS, RECEIVE, TransmitFifo Mode Registers applicable only in Fifo mode Serial Communications Interface SCI Module SCI-A Registers1 SCI-B Registers110. Serial Communications Interface SCI Module Block Diagram −−−−−Serial Peripheral Interface SPI Module 10. SPI Registers1 −−−−− −−−−−11. Gpio Mux Registers1 2 Register Description12. Gpio Data Registers1 PIN Hardware Development Tools Device and Development Support Tool NomenclatureSoftware Development Tools Documentation Support SM320F2812-HT Absolute Maximum Ratings Value UnitMIN NOM MAX Unit Electrical CharacteristicsRecommended Operating Conditions Parameter Test Conditions MIN TYP MAX UnitDie Junction Temperature C HoursMode Test Conditions Current Consumption Graphs VddaioPeripheral Module Power Sequencing RequirementsReducing Current Consumption DD Current Reduction mASupplier Part Number Signal Transition LevelsRecommended Low-Dropout Regulators VIH 90% 10% VIL Timing Parameter SymbologyVOH 80% 20% VOL 85 pF General Notes on Timing ParametersTest Load Circuit Input Clock Requirements Clock Requirements and CharacteristicsDevice Clock Table Clock Table and NomenclatureXclkin Timing Requirements PLL Disabled1 Output Clock CharacteristicsXclkin Timing Requirements PLL Bypassed or Enabled Possible PLL Configuration Modes1Reset Timing Reset XRS Timing Requirements1XF/XPLLDIS GPIOF14Xclkout XRS XF/XPLLDIS XMP/MCGPIOF14/XF Xclkin Xclkout XRSXCLKIN/8 XCLKIN/2A0−A15 Low-Power Mode Wakeup Timing10. Idle Mode Switching Characteristics1 Xclkout = Sysclkout11. Standby Mode Switching Characteristics1 XCLKOUT² Device Status Flushing Pipeline Wake−up SignalStandby Sysclkout Cycles12. Halt Mode Switching Characteristics1 Parameter MIN TYP MAX UnitEvent Manager Interface PWM TimingParameter Test Conditions MIN 13. PWM Switching Characteristics114. Timer and Capture Unit Timing Requirements1 MAX Unit17. Interrupt Switching Characteristics Interrupt Timing18. Interrupt Timing Requirements 19. General-Purpose Output Switching CharacteristicsGeneral-Purpose Input/Output Gpio Output Timing TxCTRIP, CxTRIP PDPINTx See Note BQualprd = 1 2 x Sysclkout cycles x Output From Qualifier General-Purpose Input/Output Gpio Input TimingQualprd Sysclkout GPIOxn SPI Master Mode Timing21. SPI Master Mode External Timing Clock Phase = 01 2 Spisimo Spisomi Master In Data Must Be Valid22. SPI Master Mode External Timing Clock Phase = 11 2 SM320F2812-HTData Valid SpisomiSPI Slave Mode Timing 23. SPI Slave Mode External Timing Clock Phase = 01 2SM320F2812-HT 24. SPI Slave Mode External Timing Clock Phase = 11 2 Spisimo Data Must Be ValidSM320F2812-HT 27. Valid and Invalid Timing1 26. Xtiming Register Configuration Restrictions1External Interface Xintf Timing X2TIMING =30. Xtiming Register Configuration Restrictions1 28. Xtiming Register Configuration Restrictions129. Valid and Invalid Timing when using Synchronous XREADY1 Mode Sysclkout Xtimclk Xclkout 31. Xtiming Register Configuration Restrictions133. Xintf Clock Configurations 32. Asynchronous XREADY128. Relationship Between Xtimclk and Sysclkout XINTCNF2 Clkoff Xtimclk ClkmodeXintf Signal Alignment to Xclkout XR/WXCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk External Interface Read Timing35. External Memory Interface Read Timing Requirements1 XZCS0AND1, XZCS2 XZCS6AND7XCLKOUT=XTIMCLK External Interface Write TimingLead Active DoutSM320F2812-HT Setup time, Xready Synch low before Xclkout high/low XREADYSynch WS Synch Active Lead TrailDIN XREADYAsynch WS AsynchXCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk XZCS0AND1, XZCS2 Parameter MIN MAX Unit 33. Write With Synchronous Xready Access 34. Write With Asynchronous Xready Access Xhold and Xholda XWE, XRD XZCS6AND7 XR/WXR/W XZCS0AND1 XHOLD/XHOLDA Timing44. XHOLD/XHOLDA Timing Requirements Xclkout = XTIMCLK1 2 XZCS2 XZCS6AND7XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 Xtimclk 36. XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 XtimclkOn-Chip Analog-to-Digital Converter ADC Absolute Maximum Ratings46. DC Specifications1 MIN TYP MAX 47. AC Specifications148. Current Consumption1 TYP ADC Operating MODE/CONDITIONSPwdnbg Pwdnref ADC Power-Up Control Bit TimingADCIN0 PwdnadcSequential Sampling Mode Single Channel Smode = Detailed DescriptionClock Remarks 50. Sequential Sampling Mode Timing1Sample n + Simultaneous Sampling Mode Dual-Channel Smode = AT 25-MHz ADCDefinitions of Specifications and Terminology 52. McBSP Timing Requirements1 2 Multichannel Buffered Serial Port McBSP TimingMcBSP Transmit and Receive Timing Clkg + Clksrg53. McBSP Switching Characteristics1 2 Dxena =M1, M11 M2, M12 M13 M16 M18M17 M18 M19Parameter Master Slave Unit MIN MAX McBSP as SPI Master or Slave TimingMaster Slave Unit MIN MAX M39 M49 M58 Recommended Operating Conditions 63. Flash/OTP Access Timing1Flash Timing 62. Flash Parameters at 150-MHz SYSCLKOUT1250 64. Minimum Required Wait-States at Different FrequenciesWAIT-STATE Random Wait STATE2 Mechanical Data Samples Package Type Pins Package Qty Eco Plan LeadOrderable Device Page Rfid Products ApplicationsDSP