Texas Instruments SM320F2812-HT specifications Parameter MIN MAX Unit

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010www.ti.com

6.26 External Interface Ready-on-Write Timing With One External Wait State

Table 6-41. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State)(1)

PARAMETER

MIN

MAX

UNIT

td(XCOH-XZCSL)

Delay time, XCLKOUT high to zone chip-select active low

1

ns

td(XCOHL-XZCSH)

Delay time, XCLKOUT high or low to zone chip-select inactive high

–2

3

ns

td(XCOH-XA)

Delay time, XCLKOUT high to address valid

2

ns

td(XCOHL-XWEL)

Delay time, XCLKOUT high/low to

low

2

ns

XWE

td(XCOHL-XWEH)

Delay time, XCLKOUT high/low to

high

2

ns

XWE

td(XCOH-XRNWL)

low

1

ns

Delay time, XCLKOUT high to XR/W

td(XCOHL-XRNWH)

high

–2

1

ns

Delay time, XCLKOUT high/low to XR/W

ten(XD)XWEL

Enable time, data bus driven from

low

0

ns

XWE

td(XWEL-XD)

Delay time, data valid after

active low

4

ns

XWE

th(XA)XZCSH

Hold time, address valid after zone chip-select inactive high

(2)

ns

t

Hold time, write data valid after

inactive high

TW–2(3)

ns

XWE

h(XD)XWE

tdis(XD)XRNW

Data bus disabled after XR/W

inactive high

4

ns

(1)Not production tested.

(2)During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.

(3)TW = trail period, write access (see Table 6-25)

Table 6-42. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)(1) (2)

		MIN	MAX	UNIT
tsu(XRDYsynchL)XCOHL	Setup time, XREADY (Synch) low before XCLKOUT high/low	15		ns
th(XRDYsynchL)	Hold time, XREADY (Synch) low	12		ns
te(XRDYsynchH)	Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge		3	ns
tsu(XRDYsynchH)XCOHL	Setup time, XREADY (Synch) high before XCLKOUT high/low	15		ns
th(XRDYsynchH)XZCSH	Hold time, XREADY (Synch) held high after zone chip select high	0		ns

(1)Not production tested.

(2)The first XREADY (Synch) sample occurs with respect to E in Figure 6-33 :

E =(XWRLEAD + XWRACTIVE) tc(XTIM)

When first sampled, if XREADY (Synch) is found to be high, then the access completes. If XREADY (Synch) is found to be low, it is

sampled again each tc(XTIM) until it is found to be high.

For each sample, setup time from the beginning of the access can be calculated as:

D =(XWRLEAD + XWRACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.

Table 6-43. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State)(1) (2)

		MIN	MAX	UNIT
tsu(XRDYasynchL)XCOHL	Setup time, XREADY (Asynch) low before XCLKOUT high/low	11		ns
th(XRDYasynchL)	Hold time, XREADY (Asynch) low	8		ns
te(XRDYasynchH)	Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT edge		3	ns
tsu(XRDYasynchH)XCOHL	Setup time, XREADY (Asynch) high before XCLKOUT high/low	11		ns
th(XRDYasynchH)XZCSH	Hold time, XREADY (Asynch) held high after zone chip select high	0		ns

(1)Not production tested.

(2)The first XREADY (Synch) sample occurs with respect to E in Figure 6-33:

E = (XWRLEAD + XWRACTIVE – 2) tc(XTIM)

When first sampled, if XREADY (Asynch) is found to be high, then the access completes. If XREADY (Asynch) is found to be low, it is

sampled again each tc(XTIM) until it is found to be high.

For each sample, setup time from the beginning of the access can be calculated as:

D = (XWRLEAD + XWRACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.

128 Electrical SpecificationsCopyright © 2009–2010, Texas Instruments Incorporated

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