Texas Instruments specifications SM320F2812-HT Contents

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010www.ti.com

Contents

1	Features			11
	1.1	SUPPORTS EXTREME TEMPERATURE APPLICATIONS		12
2	Introduction			13
	2.1	Description		13
	2.2	Device Summary		14
	2.3	Die Layout		15
	2.4	Pin Assignments		16
	2.5	Signal Descriptions		17
3	Functional Overview			27
	3.1	Memory Map		28
	3.2	Brief Descriptions		31
		3.2.1	C28x CPU	31
		3.2.2	Memory Bus (Harvard Bus Architecture)	31
		3.2.3	Peripheral Bus	31
		3.2.4	Real-Time JTAG and Analysis	31
		3.2.5	External Interface (XINTF)	32
		3.2.6	Flash	32
		3.2.7	L0, L1, H0 SARAMs	32
		3.2.8	Boot ROM	32
		3.2.9	Security	33
		3.2.10	Peripheral Interrupt Expansion (PIE) Block	34
		3.2.11	External Interrupts (XINT1, XINT2, XINT13, XNMI)	34
		3.2.12	Oscillator and PLL	34
		3.2.13	Watchdog	34
		3.2.14	Peripheral Clocking	34
		3.2.15	Low-Power Modes	34
		3.2.16	Peripheral Frames 0, 1, 2 (PFn)	35
		3.2.17	General-Purpose Input/Output (GPIO) Multiplexer	35
		3.2.18	32-Bit CPU Timers (0, 1, 2)	35
		3.2.19	Control Peripherals	35
		3.2.20	Serial Port Peripherals	36
	3.3	Register Map		36
	3.4	Device Emulation Registers		39
	3.5	External Interface, XINTF		39
		3.5.1	Timing Registers	41
		3.5.2	XREVISION Register	41
	3.6	Interrupts		42
		3.6.1	External Interrupts	45
	3.7	System Control		46
	3.8	OSC and PLL Block		48
		3.8.1	Loss of Input Clock	49
	3.9	PLL-Based Clock Module		49
	3.10 External Reference Oscillator Clock Option			49
	3.11	Watchdog Block		50
	3.12	Low-Power Modes Block		51
2	Contents			Copyright © 2009–2010, Texas Instruments Incorporated