Texas Instruments SM320F2812-HT 6.6 Reducing Current Consumption, 6.7 Power Sequencing Requirements

SM320F2812-HT

SGUS062A–JUNE 2009 –REVISED APRIL 2010

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6.6 Reducing Current Consumption

28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current

consumption can be achieved by turning off the clock to any peripheral module which is not used in a

given application. Table 6-1 indicates the typical reduction in current consumption achieved by turning off

the clocks to various peripherals.

Table 6-1. Typical Current Consumption by Various Peripherals (at 150 MHz)(1)

(2)

PERIPHERAL MODULE IDD CURRENT REDUCTION (mA)

eCAN 12

EVA 6

EVB 6

ADC 8(3)

SCI 4

SPI 5

McBSP 13

(1) All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is

possible only after the peripheral clocks are turned on.

(2) Not production tested.

(3) This number represents the current drawn by the digital portion of the ADC module. Turning off the

clock to the ADC module results in the elimination of the current drawn by the analog portion of the

ADC (ICCA) as well.

6.7 Power Sequencing Requirements

SM320F2812 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to power up the CPU, Flash, ROM,

ADC, and the I/Os. To ensure the correct reset state for all modules during power up, there are some

requirements to be met while powering up/powering down the device. The current F2812 silicon reference

schematics (Spectrum Digital Incorporated eZdsp. board) suggests two options for the power sequencing

circuit.

• Option 1:

In this approach, an external power sequencing circuit enables VDDIO first, then VDD and VDD1 (1.8 V or

1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (VDD3VFL) and ADC (VDDA1/VDDA2/AVDDREFBG)

modules are ramped up. While option 1 is still valid, TI has simplified the requirement. Option 2 is the

recommended approach.

• Option 2:

Enable power to all 3.3-V supply pins (VDDIO, VDD3VFL, VDDA1/VDDA2/VDDAIO/AVDDREFBG) and thenramp

1.8 V (or 1.9 V) (VDD/VDD1) supply pins.

1.8 V or 1.9 V (VDD/VDD1) should not reach 0.3 V until VDDIO has reached 2.5 V. This ensures the reset

signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the

modules inside the device. See Figure 6-8 for power-on reset timing.

• Power-Down Sequencing:

During power-down, the device reset should be asserted low (8 ms, minimum) before the VDD supply

reaches 1.5 V. This helps to keep on-chip flash logic in reset prior to the VDDIO/VDD power supplies

ramping down. It is recommended that the device reset control from Low-Dropout (LDO) regulators or

voltage supervisors be used to meet this constraint. LDO regulators that facilitate power-sequencing

(with the aid of additional external components) may be used to meet the power sequencing

requirement. See www.spectrumdigital.com for F2812 eZdsp™ schematics and updates.

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