Texas Instruments SM320F2812-HT 6.24 External Interface Write Timing

Lead Active Trail

td(XCOH-XZCSL)

td(XCOH-XA)

td(XCOHL-XWEL) td(XCOHL-XWEH)

td(XCOHL-XZCSH)

ten(XD)XWEL th(XD)XWEH

tdis(XD)XRNW

XCLKOUT=XTIMCLK

XCLKOUT= 1/2 XTIMCLK

XZCS0AND1, XZCS2,

XZCS6AND7

XA[0:18]

XRD

XWE

XR/W

XD[0:15]

NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle

before an access to meet this requirement.

B. During alignment cycles, all signals transitions to their inactive state.

C. For USEREADY = 0, the external XREADY input signal is ignored.

D. XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles.

td(XCOH-XRNWL) td(XCOHL-XRNWH)

DOUT

XREADY

td(XWEL-XD)

SM320F2812-HT

www.ti.com

SGUS062A–JUNE 2009 –REVISED APRIL 2010

XTIMING register parameters used for this example:

XRDLEAD XRDACTIVE XRDTRAIL USEREADY X2TIMING XWRLEAD XWRACTIVE XWRTRAIL READYMODE

≥1≥0≥0 0 0 N/A(1) N/A (1) N/A(1) N/A(1)

(1) N/A = "Don't care" for this example

6.24 External Interface Write Timing

Table 6-36. External Memory Interface Write Switching Characteristics(1)

PARAMETER MIN MAX UNIT

td(XCOH-XZCSL) Delay time, XCLKOUT high to zone chip-select active low 1 ns

td(XCOHL-XZCSH) Delay time, XCLKOUT high or low to zone chip-select inactive high –2 3 ns

td(XCOH-XA) Delay time, XCLKOUT high to address valid 2 ns

td(XCOHL-XWEL) Delay time, XCLKOUT high/low to XWE low 2 ns

td(XCOHL-XWEH) Delay time, XCLKOUT high/low to XWE high 2 ns

td(XCOH-XRNWL) Delay time, XCLKOUT high to XR/W low 1 ns

td(XCOHL-XRNWH) Delay time, XCLKOUT high/low to XR/W high –2 1 ns

ten(XD)XWEL Enable time, data bus driven from XWE low 0 ns

td(XWEL-XD) Delay time, data valid after XWE active low 4 ns

th(XA)XZCSH Hold time, address valid after zone chip-select inactive high (2)ns

th(XD)XWE Hold time, write data valid after XWE inactive high TW–2 (3) ns

tdis(XD)XRNW Data bus disabled after XR/W inactive high 4 ns

(1) Not production tested.

(2) During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.

(3) TW = Trail period, write access. See Table 6-25 .

Figure 6-30. Example Write Access

Copyright © 2009–2010, Texas Instruments Incorporated Electrical Specifications 123

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Contents

Main SM320F2812-HT Contents SM320F2812-HT Page List of Figures Page List of Tables SM320F2812-HT Page Page Digital Signal Processor 1 Features SM320F2812-HT 1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS 2 Introduction 2.2 Device Summary Table 2-1 provides a summary of the device features. Table 2-1. Hardware Features 2.3 Die Layout XZCS6AND7 131 XF_XPLLDIS PWM7 2.4 Pin Assignments Figure 2-2. SM320F2812 172-Pin HFG CQFP (Top View) 16 Introduction 2.5 Signal Descriptions Page Page SM320F2812-HT Page Page Signal Descriptions (Continued) Page Page Page 3 Functional Overview Figure 3-1. Functional Block Diagram LEGEND: SM320F2812-HT Product Folder Link(s): SM320F2812-HT 3.1 Memory Map Figure 3-2. F2812 Memory Map (See Notes A. Through G.) 28 Functional Overview Page Page 3.2 Brief Descriptions 3.2.1 C28x CPU 3.2.2 Memory Bus (Harvard Bus Architecture) 3.2.3 Peripheral Bus 3.2.4 Real-Time JTAG and Analysis SM320F2812-HT 3.2.5 External Interface (XINTF) 3.2.6 Flash 3.2.7 L0, L1, H0 SARAMs 3.2.8 Boot ROM 3.2.9 Security 3.2.10 Peripheral Interrupt Expansion (PIE) Block 3.2.11 External Interrupts (XINT1, XINT2, XINT13, XNMI) 3.2.12 Oscillator and PLL 3.2.13 Watchdog 3.2.14 Peripheral Clocking 3.2.16 Peripheral Frames 0, 1, 2 (PFn) 3.2.17 General-Purpose Input/Output (GPIO) Multiplexer 3.2.18 32-Bit CPU Timers (0, 1, 2) 3.2.19 Control Peripherals 3.2.20 Serial Port Peripherals 3.3 Register Map Table 3-4. Peripheral Frame 0 Registers Table 3-5. Peripheral Frame 1 Registers Table 3-6. Peripheral Frame 2 Registers 3.4 Device Emulation Registers 3.5 External Interface, XINTF Figure 3-3. External Interface Block Diagram 3.5.1 Timing Registers 3.5.2 XREVISION Register 3.6 Interrupts Figure 3-4 shows how the various interrupt sources are multiplexed within the F2812 device. Figure 3-5. Multiplexing of Interrupts Using the PIE Block Table 3-10. PIE Peripheral Interrupts Table 3-11. PIE Configuration and Control Registers 3.6.1 External Interrupts Table 3-12. External Interrupts Registers 3.7 System Control Page 3.8 OSC and PLL Block Figure 3-7 shows the OSC and PLL block on the F2812. 3.8.1 Loss of Input Clock 3.9 PLL-Based Clock Module 3.10 External Reference Oscillator Clock Option 3.11 Watchdog Block 3.12 Low-Power Modes Block 4 Peripherals 4.1 32-Bit CPU-Timers 0/1/2 Page Table 4-1. CPU-Timers 0, 1, 2 Configuration and Control Registers 4.2 Event Manager Modules (EVA, EVB) Table 4-3. EVA Registers A. TheEVB module is similar to the EVA module. Figure 4-3. Event Manager A Functional Block Diagram (See Note A.) 4.2.1 General-Purpose (GP) Timers 4.2.2 Full-Compare Units 4.2.3 Programmable Deadband Generator 4.2.4 PWM Waveform Generation 4.2.5 Double Update PWM Mode 4.2.6 PWM Characteristics 4.2.7 Capture Unit 4.2.8 Quadrature-Encoder Pulse (QEP) Circuit 4.2.9 External ADC Start-of-Conversion 4.3 Enhanced Analog-to-Digital Converter (ADC) Module Page Figure 4-5. ADC Pin Connections With Internal Reference (See Notes A and B) The temperature rating of any recommended component must match the rating of the end product. Figure 4-6. ADC Pin Connections With External Reference Page 4.4 Enhanced Controller Area Network (eCAN) Module Page Figure 4-8. eCAN Memory Map Page 4.5 Multichannel Buffered Serial Port (McBSP) Module Figure 4-9. McBSP Module With FIFO Table 4-7 provides a summary of the McBSP registers. Table 4-7. McBSP Register Summary Table 4-7. McBSP Register Summary (continued) 4.6 Serial Communications Interface (SCI) Module Table 4-9. SCI-B Registers Figure 4-10 shows the SCI module block diagram. Figure 4-10. Serial Communications Interface (SCI) Module Block Diagram 4.7 Serial Peripheral Interface (SPI) Module Page Figure 4-11 is a block diagram of the SPI in slave mode. Figure 4-11. Serial Peripheral Interface Module Block Diagram (Slave Mode) 78 Peripherals 4.8 GPIO MUX Table 4-12. GPIO Data Registers SM320F2812-HT Figure 4-12. GPIO/Peripheral Pin Multiplexing 5 Development Support 5.1 Device and Development Support Tool Nomenclature 5.2 Documentation Support Page 6 Electrical Specifications 6.1 Absolute Maximum Ratings 6.2 Recommended Operating Conditions See 6.3 Electrical Characteristics Over recommended operating conditions (unless otherwise noted) Page HALT and STANDBY modes cannot be used when the PLL is disabled. 88 Electrical Specifications 6.5 Current Consumption Graphs Figure 6-2. Typical Current Consumption Over Frequency Figure 6-3. Typical Power Consumption Over Frequency 6.6 Reducing Current Consumption 6.7 Power Sequencing Requirements 6.8 Signal Transition Levels 6.9 Timing Parameter Symbology 6.10 General Notes on Timing Parameters 6.11 Test Load Circuit 6.12 Device Clock Table 6.13 Clock Requirements and Characteristics 6.13.1 Input Clock Requirements Table 6-5. XCLKIN Timing Requirements PLL Bypassed or Enabled Table 6-6. XCLKIN Timing Requirements PLL Disabled Table 6-7. Possible PLL Configuration Modes 6.13.2 Output Clock Characteristics Table 6-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) SeeNote A SeeNoteB Figure 6-8. Clock Timing 6.14 Reset Timing Table 6-9. Reset (XRS) Timing Requirements Figure 6-9. Power-on Reset in Microcomputer Mode (XMP/MC = 0) (See Note A) Figure 6-10. Power-on Reset in Microprocessor Mode (XMP/MC = 1) Figure 6-11. Warm Reset in Microcomputer Mode Figure 6-12. Effect of Writing Into PLLCR Register 6.15 Low-Power Mode Wakeup Timing Figure 6-13. IDLE Entry and Exit Timing Page Figure 6-14. STANDBY Entry and Exit Timing Table 6-12. HALT Mode Switching Characteristics Figure 6-15. HALT Wakeup Using XNMI 6.16 Event Manager Interface 6.16.1 PWM Timing PWM refers to all PWM outputs on EVA and EVB. Table 6-13. PWM Switching Characteristics Table 6-14. Timer and Capture Unit Timing Requirements Figure 6-16. PWM Output Timing Figure 6-17. TDIRx Timing Table 6-15. External ADC Start-of-Conversion EVA Switching Characteristics 6.16.2 Interrupt Timing Table 6-17. Interrupt Switching Characteristics Table 6-18. Interrupt Timing Requirements Figure 6-20. External Interrupt Timing 6.17 General-Purpose Input/Output (GPIO) Output Timing Table 6-19. General-Purpose Output Switching Characteristics Figure 6-21. General-Purpose Output Timing 6.18 General-Purpose Input/Output (GPIO) Input Timing tc(SPC) +SPI clock cycle time +LSPCLK 4or LSPCLK (SPIBRR)1) +tc(LCO) +LSPCLK cycle time (2) GPIOxn t 6.19 SPI Master Mode Timing Table 6-21. SPI Master Mode External Timing (Clock Phase = 0) Copyright 20092010, Texas Instruments Incorporated Electrical Specifications 109 Figure 6-24. SPI Master Mode External Timing (Clock Phase = 0) tc(SPC) +SPI clock cycle time +LSPCLK 4or LSPCLK (SPIBRR)1) +tc(LCO) +LSPCLK cycle time (2) Table 6-22. SPI Master Mode External Timing (Clock Phase = 1) Copyright 20092010, Texas Instruments Incorporated Electrical Specifications 111 Figure 6-25. SPI Master External Timing (Clock Phase = 1) 6.20 SPI Slave Mode Timing Table 6-23. SPI Slave Mode External Timing (Clock Phase = 0) Figure 6-26. SPI Slave Mode External Timing (Clock Phase = 0) Page Table 6-24. SPI Slave Mode External Timing (Clock Phase = 1) Figure 6-27. SPI Slave Mode External Timing (Clock Phase = 1) Page 6.21 External Interface (XINTF) Timing Page or Table 6-31. XTIMING Register Configuration Restrictions Examples of valid and invalid timing when using Asynchronous XREADY: Table 6-32. Asynchronous XREADY The relationship between SYSCLKOUT and XTIMCLK is shown in Figure 6-28. Figure 6-28. Relationship Between XTIMCLK and SYSCLKOUT 6.22 XINTF Signal Alignment to XCLKOUT 6.23 External Interface Read Timing Table 6-34. External Memory Interface Read Switching Characteristics Table 6-35. External Memory Interface Read Timing Requirements Figure 6-29. Example Read Access 6.24 External Interface Write Timing Table 6-36. External Memory Interface Write Switching Characteristics Figure 6-30. Example Write Access Page 6.25 External Interface Ready-on-Read Timing With One External Wait State Table 6-37. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) Table 6-38. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) Table 6-39. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) Table 6-40. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) Table 6-40. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) (continued) Figure 6-31. Example Read With Synchronous XREADY Access Figure 6-32. Example Read With Asynchronous XREADY Access 6.26 External Interface Ready-on-Write Timing With One External Wait State Table 6-41. External Memory Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) Table 6-42. Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) Table 6-43. Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) Figure 6-33. Write With Synchronous XREADY Access Figure 6-34. Write With Asynchronous XREADY Access 6.27 XHOLDand XHOLDA 6.28 XHOLD/XHOLDATiming Table 6-44. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) Figure 6-35. External Interface Hold Waveform Table 6-45. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) Figure 6-36. XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) 6.29 On-Chip Analog-to-Digital Converter 6.29.1 ADC Absolute Maximum Ratings 6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions Table 6-46. DC Specifications Table 6-47. AC Specifications 6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) Table 6-48. Current Consumption Figure 6-37. ADC Analog Input Impedance Model 6.29.4 ADC Power-Up Control Bit Timing Figure 6-38. ADC Power-Up Control Bit Timing Table 6-49. ADC Power-Up Delays 6.29.5 Detailed Description 6.29.6 Sequential Sampling Mode (Single Channel) (SMODE = 0) Table 6-50. Sequential Sampling Mode Timing 6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) Figure 6-40. Simultaneous Sampling Mode Timing Table 6-51. Simultaneous Sampling Mode Timing 6.29.8 Definitions of Specifications and Terminology 6.30 Multichannel Buffered Serial Port (McBSP) Timing 6.30.1 McBSP Transmit and Receive Timing Table 6-52. McBSP Timing Requirements Table 6-53. McBSP Switching Characteristics Figure 6-41. McBSP Receive Timing Figure 6-42. McBSP Transmit Timing 6.30.2 McBSP as SPI Master or Slave Timing Table 6-54. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) Table 6-55. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0) Figure 6-43. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) Table 6-57. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0) Figure 6-44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1) Figure 6-45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 Table 6-60. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) Table 6-61. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) Figure 6-46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 6.31 Flash Timing 6.31.1 Recommended Operating Conditions Table 6-62. Flash Parameters at 150-MHz SYSCLKOUT Table 6-63. Flash/OTP Access Timing Table 6-64. Minimum Required Wait-States at Different Frequencies Table 6-64. Minimum Required Wait-States at Different Frequencies (1) (continued) 7 Mechanical Data PACKAGE OPTION ADDENDUM PACKAGING INFORMATION Page IMPORTANT NOTICE