SM320F2812-HT

www.ti.comSGUS062A –JUNE 2009 –REVISED APRIL 2010

XTIMING register parameters used for this example:

XRDLEAD

XRDACTIVE

XRDTRAIL

USEREADY

X2TIMING

XWRLEAD

XWRACTIVE

XWRTRAIL

READYMODE

 

 

 

 

 

 

 

 

 

1

0

0

0

0

N/A(1)

N/A(1)

N/A(1)

N/A(1)

(1)N/A = "Don't care" for this example

6.24 External Interface Write Timing

Table 6-36. External Memory Interface Write Switching Characteristics(1)

 

PARAMETER

MIN

MAX

UNIT

 

 

 

 

 

td(XCOH-XZCSL)

Delay time, XCLKOUT high to zone chip-select active low

 

1

ns

td(XCOHL-XZCSH)

Delay time, XCLKOUT high or low to zone chip-select inactive high

–2

3

ns

td(XCOH-XA)

Delay time, XCLKOUT high to address valid

 

2

ns

td(XCOHL-XWEL)

Delay time, XCLKOUT high/low to

 

 

 

 

 

low

 

2

ns

XWE

 

td(XCOHL-XWEH)

Delay time, XCLKOUT high/low to

 

 

 

 

 

high

 

2

ns

XWE

 

td(XCOH-XRNWL)

 

 

 

 

 

 

 

 

low

 

1

ns

Delay time, XCLKOUT high to XR/W

 

td(XCOHL-XRNWH)

 

 

 

 

 

 

 

 

 

 

 

 

 

high

–2

1

ns

Delay time, XCLKOUT high/low to XR/W

ten(XD)XWEL

Enable time, data bus driven from

 

 

 

 

 

 

low

0

 

ns

XWE

 

td(XWEL-XD)

Delay time, data valid after

 

 

 

active low

 

4

ns

XWE

 

t

Hold time, address valid after zone chip-select inactive high

 

 

(2)ns

h(XA)XZCSH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

Hold time, write data valid after

 

 

 

 

 

 

inactive high

TW–2(3)

 

ns

XWE

 

h(XD)XWE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tdis(XD)XRNW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data bus disabled after XR/W

inactive high

4

 

ns

(1)Not production tested.

(2)During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.

(3)TW = Trail period, write access. See Table 6-25 .

Lead

Active

Trail

 

 

 

XCLKOUT=XTIMCLK

 

 

XCLKOUT= 1/2 XTIMCLK

 

 

td(XCOH-XZCSL)

 

td(XCOHL-XZCSH)

XZCS0AND1, XZCS2,

 

 

XZCS6AND7

 

 

td(XCOH-XA)

 

 

XA[0:18]

 

 

XRD

 

 

 

td(XCOHL-XWEL)

td(XCOHL-XWEH)

XWE

 

td(XCOHL-XRNWH)

t

 

d(XCOH-XRNWL)

 

 

XR/W

 

 

td(XWEL-XD)

 

tdis(XD)XRNW

ten(XD)XWEL

 

th(XD)XWEH

XD[0:15]

 

DOUT

 

 

XREADY

 

 

NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device inserts an alignment cycle before an access to meet this requirement.

B.During alignment cycles, all signals transitions to their inactive state.

C.For USEREADY = 0, the external XREADY input signal is ignored.

D.XA[0:18] holds the last address put on the bus during inactive cycles, including alignment cycles.

Figure 6-30. Example Write Access

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Texas Instruments SM320F2812-HT specifications External Interface Write Timing, Lead Active, Xclkout=Xtimclk, Dout

SM320F2812-HT specifications

The Texas Instruments SM320F2812-HT is a highly capable digital signal processor (DSP) specifically designed for high-performance and real-time applications in harsh environments. This part of the C2000 family of microcontrollers caters to applications in areas such as industrial automation, motor control, and power conversion, where reliability and durability under extreme temperature conditions are paramount.

One of the standout features of the SM320F2812-HT is its robust architecture based on a 32-bit fixed-point core. This allows for efficient execution of complex algorithms while maintaining a high processing speed. The processor operates at clock speeds of up to 150 MHz, enabling it to handle multiple tasks simultaneously with minimal latency.

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