Texas Instruments SM320F2812-HT specifications Xclkin Xclkout XRS, XCLKIN/8, GPIOF14/XF, XCLKIN/2

SM320F2812-HT

www.ti.com SGUS062A –JUNE 2009 –REVISED APRIL 2010

XCLKIN

X1

XCLKOUT

XRS

Address/Data/

Control

XF/XPLLDIS

XMP/MC

Boot-Mode Pins

I/O Pins

		XCLKIN/8
(XCLKIN * 5)		User-Code Dependent
	tw(RSL2)
	td(EX)	User-Code Execution Phase
User-Code Execution	(Don't Care)
	tsu(XPLLDIS)	th(XPLLDIS)
GPIOF14/XF	(Don't Care)	GPIOF14
	XPLLDIS Sampling	User-Code Dependent
(Don't Care)	th(XMP/MC)	(Don't Care)
	Boot-ROM Execution Starts	th(boot-mode)(see Note A)
Peripheral/GPIO Function	GPIO Pins as Input	Peripheral/GPIO Function
		User-Code Execution Starts
User-Code Dependent	GPIO Pins as Input (State Depends on Internal PU/PD)
		User-Code Dependent

A.After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM execution time for proper selection of Boot modes. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT is based on user environment and could be with or without PLL enabled.

Figure 6-11. Warm Reset in Microcomputer Mode

X1/XCLKIN

Write to PLLCR

SYSCLKOUT

XCLKIN x 2	XCLKIN/2	XCLKIN x 4
(Current CPU	(CPU Frequency While PLL is Stabilizing	(Changed CPU Frequency)
Frequency)	With the Desired Frequency. This Period
	(PLL Lock-up Time, tp) is
	131072 XCLKIN Cycles Long.)

Figure 6-12. Effect of Writing Into PLLCR Register

Copyright © 2009–2010, Texas Instruments Incorporated	Electrical Specifications	99
	Submit Documentation Feedback

Product Folder Link(s): SM320F2812-HT