Texas Instruments SM320F2812-HT specifications SPI Slave Mode External Timing Clock Phase = 11 2

Models: SM320F2812-HT

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SM320F2812-HT

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SGUS062A –JUNE 2009 –REVISED APRIL 2010

 

 

Table 6-24. SPI Slave Mode External Timing (Clock Phase = 1)(1) (2) (3)

 

 

 

 

 

 

 

 

 

NO.

 

 

 

MIN

MAX

UNIT

 

 

 

 

 

 

 

12

 

tc(SPC)S

Cycle time, SPICLK

8tc(LCO)

 

ns

13(4)

 

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 0)

0.5tc(SPC)S – 10

0.5tc(SPC)S

ns

 

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 1)

0.5tc(SPC)S – 10

0.5tc(SPC)S

 

 

 

14(4)

 

tw(SPCL)S

Pulse duration, SPICLK low (clock polarity = 0)

0.5tc(SPC)S – 10

0.5tc(SPC)S

ns

 

tw(SPCH)S

Pulse duration, SPICLK high (clock polarity = 1)

0.5tc(SPC)S – 10

0.5tc(SPC)S

 

 

 

 

 

tsu(SOMI-SPCH)S

Setup time, SPISOMI before SPICLK high (clock polarity =

0.125tc(SPC)S

 

 

17(4)

 

0)

 

ns

 

tsu(SOMI-SPCL)S

Setup time, SPISOMI before SPICLK low (clock polarity =

0.125tc(SPC)S

 

 

 

 

 

 

 

1)

 

 

 

 

tv(SPCH-SOMI)S

Valid time, SPIS OMI data valid after SPICLK high

0.75tc(SPC)S

 

 

18(4)

 

(clock polarity = 0)

 

ns

 

tv(SPCL-SOMI)S

Valid time, SPISOMI data valid after SPICLK low

0.75tc(SPC)S

 

 

 

 

 

 

 

(clock polarity = 1)

 

 

 

 

tsu(SIMO-SPCH)S

Setup time, SPISIMO before SPICLK high (clock polarity =

0

 

 

21(4)

 

0)

 

ns

 

tsu(SIMO-SPCL)S

Setup time, SPISIMO before SPICLK low (clock polarity =

0

 

 

 

 

 

 

 

1)

 

 

 

 

tv(SPCH-SIMO)S

Valid time, SPISIMO data valid after SPICLK high

0.5tc(SPC)S

 

 

22(4)

 

(clock polarity = 0)

 

ns

 

tv(SPCL-SIMO)S

Valid time, SPISIMO data valid after SPICLK low

0.5tc(SPC)S

 

 

 

 

 

 

 

(clock polarity = 1)

 

 

(1)The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.

t

c(SPC)

+ SPI clock cycle time +

LSPCLK or

LSPCLK

 

+ t

c(LCO)

+ LSPCLK cycle time

(SPIBRR ) 1)

(2)

 

4

 

 

 

 

 

 

 

 

 

 

(3)Not production tested.

(4)The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

12

SPICLK (clock polarity = 0)

13

14

SPICLK (clock polarity = 1)

 

17

 

 

18

 

SPISOMI

SPISOMI Data Is Valid

Data Valid

 

21

 

 

 

22

SPISIMO

SPISIMO Data

 

Must Be Valid

 

 

 

SPISTE (see Note A)

A.In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.

Figure 6-27. SPI Slave Mode External Timing (Clock Phase = 1)

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Texas Instruments SM320F2812-HT SPI Slave Mode External Timing Clock Phase = 11 2, Spisimo Data Must Be Valid

SM320F2812-HT specifications

The Texas Instruments SM320F2812-HT is a highly capable digital signal processor (DSP) specifically designed for high-performance and real-time applications in harsh environments. This part of the C2000 family of microcontrollers caters to applications in areas such as industrial automation, motor control, and power conversion, where reliability and durability under extreme temperature conditions are paramount.

One of the standout features of the SM320F2812-HT is its robust architecture based on a 32-bit fixed-point core. This allows for efficient execution of complex algorithms while maintaining a high processing speed. The processor operates at clock speeds of up to 150 MHz, enabling it to handle multiple tasks simultaneously with minimal latency.

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