Block
Start Address
Low 64K
(24x/240x Equivalent Data Space)
0x00 0000 M0 Vector − RAM (32 × 32)
(Enabled if VMAP = 0)
Data Space Prog Space
M0 SARAM (1K × 16)
M1 SARAM (1K × 16)
Peripheral Frame 0
(2K × 16)
0x00 0040
0x00 0400
0x00 0800
PIE Vector - RAM
(256 × 16)
(Enabled if VMAP
= 1, ENPIE = 1)
Reserved
Reserved
Reserved
L0 SARAM (4K × 16, Secure Block)
Peripheral Frame 1
(4K × 16, Protected) Reserved
Peripheral Frame 2
(4K × 16, Protected)
L1 SARAM (4K × 16, Secure Block)
Reserved
OTP (or ROM) (1K × 16, Secure Block)
Flash (or ROM) (128K × 16, Secure Block)
128-Bit Password
H0 SARAM (8K × 16)
Reserved
Boot ROM (4K × 16)
(Enabled if MP/MC = 0)
BROM Vector - ROM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 0, ENPIE = 0)
0x00 0D00
0x00 0E00
0x00 2000
0x00 6000
0x00 7000
0x00 8000
0x00 9000
0x00 A000
0x3D 7800
0x3D 7C00
0x3F 7FF8
0x3F 8000
0x3F A000
0x3F F000
0x3F FFC0
High 64K
(24x/240x Equivalent
Program Space)
Data Space Prog Space
Reserved
XINTF Zone 0 (8K × 16, XZCS0AND1)
XINTF Zone 1 (8K × 16, XZCS0AND1) (Protected)
Reserved
XINTF Zone 2 (0.5M × 16, XZCS2)
XINTF Zone 6 (0.5M × 16, XZCS6AND7)
Reserved
XINTF Zone 7 (16K × 16, XZCS6AND7)
(Enabled if MP/MC = 1)
XINTF Vector - RAM (32 × 32)
(Enabled if VMAP = 1, MP/MC = 1, ENPIE = 0)
On-Chip Memory External Memory XINTF
Only one of these vector maps—M0 vector, PIE vector, BROM vector, XINTF vector—should be enabled at a time.
LEGEND:
0x08 0000
0x00 4000
0x10 0000
0x18 0000
0x3F C000
0x00 2000
Reserved (1K)
0x3D 8000
SM320F2812-HT
SGUS062A–JUNE 2009 –REVISED APRIL 2010
www.ti.com

3.1 Memory Map

A. Memoryblocks are not to scale.
B. Reservedlocations are reserved for future expansion. Application should not access these areas.
C. BootROM and Zone 7 memory maps are active either in on-chip or XINTF zone depending on MP/MC, not in both.
D. PeripheralFrame 0, Peripheral Frame 1, and Peripheral Frame 2 memory maps are restricted to data memory only.
User program cannot access these memory maps in program space.
E. Protectedmeans the order of Write followed by Read operations is preserved rather than the pipeline order.
F. Certain memory ranges are EALLOW protected against spurious writes after configuration.
G. Zones 0 and 1 and Zones 6 and 7 share the same chip select; hence, these memory blocks have mirrored locations.

Figure 3-2. F2812 Memory Map (See Notes A. Through G.)

28 Functional Overview Copyright© 2009–2010, Texas Instruments Incorporated
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