Texas Instruments SM320F2812-HT specifications Watchdog Block

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010 www.ti.com

•CL1 = CL2 = 24 pF

•Cshunt = 6 pF

•ESR range = 25 to 40 Ω

3.11Watchdog Block

The watchdog block on the F2812 is identical to the one used on the 240x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which resets the watchdog counter. Figure 3-9shows the various functional blocks within the watchdog module.

WDCR (WDPS(2:0))

WDCR (WDDIS)

					WDCNTR(7:0)
OSCCLK	/512	Watchdog	WDCLK		8-Bit
		Prescaler			Watchdog
					Counter
					CLR
				Clear Counter
Internal
Pullup
	WDKEY(7:0)	Bad Key			Generate	WDRST
	Watchdog
					Output Pulse	WDINT
	55 + AA
		Good Key			(512 OSCCLKs)
	Key Detector
XRS
		Core-reset		Bad	SCSR (WDENINT)
				WDCHK
		WDCR (WDCHK(2:0))		Key

WDRST

(See Note A)

1

0

1

A.The WDRST signal is driven low for 512 OSCCLK cycles.

Figure 3-9. Watchdog Module

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode timer.

In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the watchdog. The WATCHDOG module runs off the PLL clock or the oscillator clock. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.12, Low-Power Modes Block, for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode.

In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the WATCHDOG.

50 Functional OverviewCopyright © 2009–2010, Texas Instruments Incorporated

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