Texas Instruments SM320F2812-HT XHOLD/XHOLDA Timing, XR/W XZCS0AND1, XZCS2 XZCS6AND7

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010 www.ti.com

6.28XHOLD/XHOLDA Timing

Table 6-44. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK)(1) (2) (3)

									MIN	MAX	UNIT
td(HL–HiZ)	Delay time,		low to Hi–Z on all Address, Data, and Control							4tc(XTIM)	ns
		XHOLD
td(HL–HAL)	Delay time,			low to			low			5tc(XTIM)	ns
		XHOLD			XHOLDA
td(HH–HAH)	Delay time,			high to				high		3tc(XTIM)	ns
		XHOLD				XHOLDA
td(HH–BV)	Delay time,			high to Bus valid						4tc(XTIM)	ns
		XHOLD

(1)When a low signal is detected on XHOLD, all pending XINTF accesses are completed before the bus is placed in a high-impedance state.

(2)The state of XHOLD is latched on the rising edge of XTIMCLK.

(3)Not production tested.

XCLKOUT (/1 Mode)

td(HL-Hiz)

XHOLD

td(HH-HAH)

XHOLDA

td(HL-HAL) td(HH-BV)

XR/W,

XZCS0AND1,

High-Impedance

XZCS2,

XZCS6AND7

XA[18:0]	Valid	High-Impedance	Valid
XD[15:0]	Valid
	See Note A		See Note B

A.All pending XINTF accesses are completed.

B.Normal XINTF operation resumes.

Figure 6-35. External Interface Hold Waveform

132 Electrical SpecificationsCopyright © 2009–2010, Texas Instruments Incorporated

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