Texas Instruments SM320F2812-HT ADCINA70, ADCINB70, Adclo, Adcbgrefin ², Adcresext, Adcrefp

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010 www.ti.com

Figure 4-5shows the ADC pin-biasing for internal reference and Figure 4-6shows the ADC pin-biasing for external reference.

ADC 16-Channel Analog Inputs	ADCINA[7:0]	Analog input 0−3 V with respect to ADCLO
	ADCINB[7:0]
Test Pin	ADCLO	Connect to Analog Ground
	ADCBGREFIN²

ADC External Current Bias Resistor	ADCRESEXT	24.9 kW/20 kW (See Note C)
		10 mF³
ADC Reference Positive Output	ADCREFP
		10 mF³	ADCREFP and ADCREFM should not
ADC Reference Medium Output	ADCREFM
			be loaded by external circuitry
	VDDA1		Analog 3.3 V
ADC Analog Power	VDDA2		Analog 3.3 V
	VSSA1
	VSSA2
ADC Reference Power	AVDDREFBG		Analog 3.3 V
	AVSSREFBG
ADC Analog I/O Power	VDDAIO		Analog 3.3 V
	VSSAIO		Analog Ground

ADC Digital Power	VDD1		1.8 V can use the same 1.8 V (or 1.9 V) supply as the
	VSS1	Digital Ground		digital core but separate the two with a ferrite
				bead or a filter

²Provide access to this pin in PCB layouts. Intended for test purposes only. ³ TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent

NOTES: A. External decoupling capacitors are recommended on all power pins.

B.Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.

C.Use 24.9 kΩ for ADC clock range 1 − 18.75 MHz; use 20 k Ω for ADC clock range 18.75 − 25 MHz.

Figure 4-5. ADC Pin Connections With Internal Reference (See Notes A and B)

NOTE

The temperature rating of any recommended component must match the rating of the end product.

62 Peripherals Copyright © 2009–2010, Texas Instruments Incorporated

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