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Texas Instruments SM320F2812-HT specifications External Interrupts Registers

Models: SM320F2812-HT

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SM320F2812-HT

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SGUS062A –JUNE 2009 –REVISED APRIL 2010

3.6.1External Interrupts

Table 3-12. External Interrupts Registers

NAME	ADDRESS	SIZE (× 16)	DESCRIPTION

XINT1CR	0x00 7070	1	XINT1 control register

XINT2CR	0x00 7071	1	XINT2 control register

reserved	0x00 7072	5
reserved	0x00 7076	5
	0x00 7076
XNMICR	0x00 7077	1	XNMI control register

XINT1CTR	0x00 7078	1	XINT1 counter register

XINT2CTR	0x00 7079	1	XINT2 counter register

reserved	0x00 707A	5
reserved	0x00 707E	5
	0x00 707E
XNMICTR	0x00 707F	1	XNMI counter register

Each external interrupt can be enabled/disabled or qualified using positive or negative going edge. For more information, see the TMS320x281x System Control and Interrupts Reference Guide (SPRU078).

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Texas Instruments SM320F2812-HT specifications External Interrupts Registers

Contents

Data Manual SM320F2812-HT Contents Peripherals SM320F2812-HTSPI Slave Mode Timing List of Figures General-Purpose Input Timing List of Tables Interrupt Switching Characteristics 149 Copyright 2009-2010, Texas Instruments Incorporated Check for Samples SM320F2812-HT Digital Signal ProcessorSupports Extreme Temperature Applications Description IntroductionFeature Hardware FeaturesDevice Summary F2812DIE PAD Backside DIE Size DIE PAD Size Die LayoutCoordinates Thickness Finish Potential 55.0 x 64.0 μmSM320F2812 172-Pin HFG Cqfp Top View Pin AssignmentsSignal Descriptions1 Signal DescriptionsCenter Description HFG Xintf Signals PIN no DIE PADCenter Description HFG Signal DescriptionsCenter Description HFG Jtag and Miscellaneous Signals TCK TrstTMS TDICenter Description HFG ADC Analog Input Signals Center Description HFG Power Signals Gpiob or EVB Signals SM320F2812-HTPeripheral PIN no DIE PAD Gpio DIE PAD no Gpiod or EVA Signals Signal HFG CenterGpiod or EVB Signals Gpioe or Interrupt SignalsSignal HFG Center Gpiof or can Signals Gpiof or McBSP SignalsGpiof or XF CPU Output Signal Signal HFG Center Gpiog or SCI-B Signals GPIOG4 Scitxdb OGPIOG5 Scirxdb Functional Overview F2812 Memory Map See Notes A. Through G Memory MapAddress Range Program and Data Space Addresses of Flash Sectors in F2812Area Wait StatesComments H0 Saram1 C28x CPU Brief DescriptionsMemory Bus Harvard Bus Architecture Peripheral BusExternal Interface Xintf Boot ROMFlash 7 L0, L1, H0 SARAMsBoot Mode Selected GPIOF4 GPIOF12 GPIOF3 GPIOF2 Boot Mode SelectionSecurity Code Security Module DisclaimerPeripheral Interrupt Expansion PIE Block Low-Power ModesExternal Interrupts XINT1, XINT2, XINT13, Xnmi Oscillator and PLLPeripheral Frames 0, 1, 2 PFn 18 32-Bit CPU Timers 0, 1General-Purpose Input/Output Gpio Multiplexer Control PeripheralsRegister Map Serial Port PeripheralsPeripheral Frame 0 Registers1 Access TypePeripheral Frame 1 Registers1 Name Address RangePeripheral Frame 2 Registers1 Device Emulation Registers External Interface, XintfDevice Emulation Registers XZCS2 XZCS0XZCS0AND1 XZCS1XZCS6 XZCS6AND7 XZCS7 XWE XRD XR/W Xready XMP/MC Xhold Xholda XclkoutTiming Registers Xintf Configuration and Control Register MappingsXrevision Register Xrevision Register Bit DefinitionsInterrupts INT1 INT2 INT11 INT12 IntmCPU PIE Interrupts 11. PIE Configuration and Control Registers1 12. External Interrupts Registers External InterruptsSystem Control Clock and Reset Domains13. PLL, Clocking, Watchdog, and Low-Power Mode Registers1 14. Pllcr Register Bit Definitions OSC and PLL BlockLoss of Input Clock PLL Mode Remarks SysclkoutPLL-Based Clock Module External Reference Oscillator Clock OptionWatchdog Block 16. F2812 Low-Power Modes Low-Power Modes BlockMode Oscclk Clkin SysclkoutTddrhtddr 32-Bit CPU-Timers 0/1/2Prdhprd Pschpsc TCR.4INT13 PIE TINT1 TINT0 CPU-TIMER INT1 to INT12 C28xINT14 XINT13 TINT2 CPU-Timers 0, 1, 2 Configuration and Control Registers Module and Signal Names for EVA and EVB Event Manager Modules EVA EVB SignalEvent Manager Modules EVA, EVB EVA Registers1 Event Manager a Functional Block Diagram See Note a Double Update PWM Mode General-Purpose GP TimersFull-Compare Units Programmable Deadband GeneratorCapture Unit PWM CharacteristicsQuadrature-Encoder Pulse QEP Circuit External ADC Start-of-ConversionEnhanced Analog-to-Digital Converter ADC Module MUX ADCINA0 Adcenclk HspclkADCINA7 ADCADCINB70 ADCINA70Adclo Adcbgrefin ²SM320F2812-HT Adclo AdcbgrefinAvddrefbg Avssrefbg ADC Registers1 Enhanced Controller Area Network eCAN Module Unit SN65HVD23xCan Bus ECAN Memory Map Register Name Address Can Registers Map1Multichannel Buffered Serial Port McBSP Module Where Clksrg source could be LSPCLK, CLKX, or CLKR.2Lspclk TX FifoFSX ClkxMcBSP Register Summary Name Address Type Reset Value DescriptionHEX Data REGISTERS, RECEIVE, TransmitFifo Mode Registers applicable only in Fifo mode Serial Communications Interface SCI Module SCI-B Registers1 SCI-A Registers1−−−−− 10. Serial Communications Interface SCI Module Block DiagramSerial Peripheral Interface SPI Module 10. SPI Registers1 −−−−− −−−−−Register Description 11. Gpio Mux Registers1 212. Gpio Data Registers1 PIN Device and Development Support Tool Nomenclature Software Development ToolsHardware Development Tools Documentation Support SM320F2812-HT Value Unit Absolute Maximum RatingsRecommended Operating Conditions Electrical CharacteristicsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX UnitHours Die Junction Temperature CMode Test Conditions Vddaio Current Consumption GraphsReducing Current Consumption Power Sequencing RequirementsPeripheral Module DD Current Reduction mASignal Transition Levels Recommended Low-Dropout RegulatorsSupplier Part Number Timing Parameter Symbology VOH 80% 20% VOLVIH 90% 10% VIL General Notes on Timing Parameters Test Load Circuit85 pF Device Clock Table Clock Requirements and CharacteristicsInput Clock Requirements Clock Table and NomenclatureXclkin Timing Requirements PLL Bypassed or Enabled Output Clock CharacteristicsXclkin Timing Requirements PLL Disabled1 Possible PLL Configuration Modes1Reset XRS Timing Requirements1 Reset TimingGPIOF14 XF/XPLLDISXF/XPLLDIS XMP/MC Xclkout XRSXCLKIN/8 Xclkin Xclkout XRSGPIOF14/XF XCLKIN/210. Idle Mode Switching Characteristics1 Low-Power Mode Wakeup TimingA0−A15 Xclkout = Sysclkout11. Standby Mode Switching Characteristics1 Standby Device Status Flushing Pipeline Wake−up SignalXCLKOUT² Sysclkout CyclesParameter MIN TYP MAX Unit 12. Halt Mode Switching Characteristics1PWM Timing Event Manager Interface14. Timer and Capture Unit Timing Requirements1 13. PWM Switching Characteristics1Parameter Test Conditions MIN MAX UnitInterrupt Timing 17. Interrupt Switching CharacteristicsGeneral-Purpose Input/Output Gpio Output Timing 19. General-Purpose Output Switching Characteristics18. Interrupt Timing Requirements TxCTRIP, CxTRIP PDPINTx See Note BGeneral-Purpose Input/Output Gpio Input Timing Qualprd SysclkoutQualprd = 1 2 x Sysclkout cycles x Output From Qualifier SPI Master Mode Timing 21. SPI Master Mode External Timing Clock Phase = 01 2GPIOxn Spisomi Master In Data Must Be Valid SpisimoSM320F2812-HT 22. SPI Master Mode External Timing Clock Phase = 11 2Spisomi Data Valid23. SPI Slave Mode External Timing Clock Phase = 01 2 SPI Slave Mode TimingSM320F2812-HT Spisimo Data Must Be Valid 24. SPI Slave Mode External Timing Clock Phase = 11 2SM320F2812-HT External Interface Xintf Timing 26. Xtiming Register Configuration Restrictions127. Valid and Invalid Timing1 X2TIMING =28. Xtiming Register Configuration Restrictions1 29. Valid and Invalid Timing when using Synchronous XREADY130. Xtiming Register Configuration Restrictions1 33. Xintf Clock Configurations 31. Xtiming Register Configuration Restrictions1Mode Sysclkout Xtimclk Xclkout 32. Asynchronous XREADY1XINTCNF2 Clkoff Xtimclk Clkmode 28. Relationship Between Xtimclk and SysclkoutXR/W Xintf Signal Alignment to Xclkout35. External Memory Interface Read Timing Requirements1 External Interface Read TimingXCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk XZCS0AND1, XZCS2 XZCS6AND7Lead Active External Interface Write TimingXCLKOUT=XTIMCLK DoutSM320F2812-HT Setup time, Xready Synch low before Xclkout high/low WS Synch Active Lead Trail DINXREADYSynch WS Asynch XCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk XZCS0AND1, XZCS2XREADYAsynch Parameter MIN MAX Unit 33. Write With Synchronous Xready Access 34. Write With Asynchronous Xready Access XWE, XRD XZCS6AND7 XR/W Xhold and Xholda44. XHOLD/XHOLDA Timing Requirements Xclkout = XTIMCLK1 2 XHOLD/XHOLDA TimingXR/W XZCS0AND1 XZCS2 XZCS6AND736. XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 Xtimclk XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 XtimclkADC Absolute Maximum Ratings On-Chip Analog-to-Digital Converter46. DC Specifications1 48. Current Consumption1 47. AC Specifications1MIN TYP MAX TYP ADC Operating MODE/CONDITIONSADCIN0 ADC Power-Up Control Bit TimingPwdnbg Pwdnref PwdnadcDetailed Description Sequential Sampling Mode Single Channel Smode =50. Sequential Sampling Mode Timing1 Sample n +Clock Remarks AT 25-MHz ADC Simultaneous Sampling Mode Dual-Channel Smode =Definitions of Specifications and Terminology McBSP Transmit and Receive Timing Multichannel Buffered Serial Port McBSP Timing52. McBSP Timing Requirements1 2 Clkg + ClksrgDxena = 53. McBSP Switching Characteristics1 2M17 M18 M16 M18M1, M11 M2, M12 M13 M19McBSP as SPI Master or Slave Timing Master Slave Unit MIN MAXParameter Master Slave Unit MIN MAX M39 M49 M58 Flash Timing 63. Flash/OTP Access Timing1Recommended Operating Conditions 62. Flash Parameters at 150-MHz SYSCLKOUT164. Minimum Required Wait-States at Different Frequencies WAIT-STATE Random Wait STATE2250 Mechanical Data Package Type Pins Package Qty Eco Plan Lead Orderable DeviceSamples Page Products Applications DSPRfid