Texas Instruments SM320F2812-HT Setup time, Xready Synch low before Xclkout high/low

SM320F2812-HT

www.ti.comSGUS062A –JUNE 2009 –REVISED APRIL 2010

6.25 External Interface Ready-on-Read Timing With One External Wait State

Table 6-37. External Memory Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State)(1)

	PARAMETER				MIN	MAX	UNIT
td(XCOH-XZCSL)	Delay time, XCLKOUT high to zone chip-select active low					1	ns
td(XCOHL-XZCSH)	Delay time, XCLKOUT high/low to zone chip-select inactive high				–2	3	ns
td(XCOH-XA)	Delay time, XCLKOUT high to address valid					2	ns
td(XCOHL-XRDL)	Delay time, XCLKOUT high/low to		active low			1	ns
		XRD
td(XCOHL-XRDH	Delay time, XCLKOUT high/low to			inactive high	–2	1	ns
		XRD
th(XA)XZCSH	Hold time, address valid after zone chip-select inactive high				(2)		ns
					(2)
th(XA)XRD	Hold time, address valid after XRD inactive high						ns

(1)Not production tested.

(2)During inactive cycles, the XINTF address bus always holds the last address put out on the bus. This includes alignment cycles.

Table 6-38. External Memory Interface Read Timing Requirements (Ready-on-Read, 1 Wait State)(1)

								MIN	MAX		UNIT
t	Access time, read data from address valid								(LR + AR) – 14	(2)	ns
a(A)
t	Access time, read data valid from					active low			AR – 12	(2)	ns
			XRD
a(XRD)
tsu(XD)XRD	Setup time, read data valid before						strobe inactive high	12			ns
				XRD
th(XD)XRD	Hold time, read data valid after				inactive high			0			ns
		XRD

(1)Not production tested.

(2)LR = Lead period, read access. AR = Active period, read access. See Table 6-25 .

Table 6-39. Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)(1) (2)

		MIN	MAX	UNIT
tsu(XRDYsynchL)XCOHL	Setup time, XREADY (Synch) low before XCLKOUT high/low	15		ns
th(XRDYsynchL)	Hold time, XREADY (Synch) low	12		ns
te(XRDYsynchH)	Earliest time XREADY (Synch) can go high before the sampling XCLKOUT edge		3	ns
tsu(XRDYsynchH)XCOHL	Setup time, XREADY (Synch) high before XCLKOUT high/low	15		ns
th(XRDYsynchH)XZCSH	Hold time, XREADY (Synch) held high after zone chip select high	0		ns

(1)Not production tested.

(2)The first XREADY (Synch) sample occurs with respect to E in Figure 6-31 :

E = (XRDLEAD + XRDACTIVE) tc(XTIM)

When first sampled, if XREADY (Synch) is found to be high, then the access completes. If XREADY (Synch) is found to be low, it is

sampled again each tc(XTIM) until it is found to be high.

For each sample (n) the setup time (D) with respect to the beginning of the access can be calculated as:

D = (XRDLEAD + XRDACTIVE + n – 1) tc(XTIM) – tsu(XRDYsynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.

Table 6-40. Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State)(1) (2)

		MIN	MAX	UNIT
tsu(XRDYAsynchL)XCOHL	Setup time, XREADY (Asynch) low before XCLKOUT high/low	11		ns
th(XRDYAsynchL)	Hold time, XREADY (Asynch) low	8		ns
te(XRDYAsynchH)	Earliest time XREADY (Asynch) can go high before the sampling XCLKOUT		3	ns
	edge

(1)Not production tested.

(2)The first XREADY (Asynch) sample occurs with respect to E in Figure 6-32 :

E = (XRDLEAD + XRDACTIVE – 2) tc(XTIM)

When first sampled, if XREADY (Asynch) is found to be high, then the access completes. If XREADY (Asynch) is found to be low, it wis

sampled again each tc(XTIM) until it is found to be high.

For each sample, setup time from the beginning of the access can be calculated as:

D = (XRDLEAD + XRDACTIVE – 3 + n) tc(XTIM) – tsu(XRDYasynchL)XCOHL where n is the sample number: n = 1, 2, 3, and so forth.

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