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Texas Instruments SM320F2812-HT Signal HFG Center, Gpiod or EVA Signals, Gpiod or EVB Signals

Models: SM320F2812-HT

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SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010www.ti.com

Signal Descriptions (Continued) (1) (continued)

PERIPHERAL

PIN NO.

DIE PAD

DIE PAD

GPIO

DIE PAD NO.

I/O/Z (2)

PU/PD (3)

DESCRIPTION

172-PIN

SIGNAL

HFG

X-CENTER

Y-CENTER

GPIOB8

CAP4_QEP3 (I)

56

64

5361.5

1428.4

I/O/Z

PU

GPIO or Capture

Input #4

GPIOB9

CAP5_QEP4 (I)

58

66

5361.5

1600.7

I/O/Z

PU

GPIO or Capture

Input #5

GPIOB10

CAP6_QEPI2 (I)

59

67

5361.5

1691.3

I/O/Z

PU

GPIO or Capture

Input #6

GPIOB11

TDIRB (I)

69

81

5361.5

2990.9

I/O/Z

PU

GPIO or Timer

Direction

GPIOB12

TCLKINB (I)

70

82

5361.5

3081.5

I/O/Z

PU

GPIO or Timer Clock

Input

GPIO or Compare 4

GPIOB13

C4TRIP (I)

60

69

5361.5

1868.1

I/O/Z

PU

Output Trip

GPIO or Compare 5

GPIOB14

C5TRIP (I)

61

71

5361.5

2044.8

I/O/Z

PU

Output Trip

GPIO or Compare 6

GPIOB15

C6TRIP (I)

62

72

5361.5

2135.4

I/O/Z

PU

Output Trip

GPIOD OR EVA SIGNALS

Timer 1 Compare

GPIOD0

T1CTRIP_PDPINTA (I)

108

123

2690.0

5057.5

I/O/Z

PU

Output Trip

Timer 2 Compare

Output Trip or

GPIOD1

T2CTRIP/EVASOC (I)

113

128

2167.8

5057.5

I/O/Z

PU

External ADC

Start-of-Conversion

EV-A

GPIOD OR EVB SIGNALS

Timer 3 Compare

GPIOD5

T3CTRIP_PDPINTB (I)

77

90

5361.5

3841.1

I/O/Z

PU

Output Trip

Timer 4 Compare

Output Trip or

GPIOD6

T4CTRIP/EVBSOC (I)

81

94

5361.5

4261.4

I/O/Z

PU

External ADC

Start-of-Conversion

EV-B

GPIOE OR INTERRUPT SIGNALS

GPIO or XINT1 or

GPIOE0

XINT1_XBIO (I)

146

164

42.6

3059.0

I/O/Z

–

XBIO input

GPIO or XINT2 or

GPIOE1

XINT2_ADCSOC (I)

148

166

42.6

2899.4

I/O/Z

–

ADC start of

conversion

GPIOE2

XNMI_XINT13 (I)

147

165

42.6

2979.2

I/O/Z

PU

GPIO or XNMI or

XINT13

GPIOF OR SPI SIGNALS

GPIOF0

SPISIMOA (O)

39

46

4709.9

42.6

I/O/Z

–

GPIO or SPI slave

in, master out

GPIOF1

SPISOMIA (I)

40

47

4805.3

42.6

I/O/Z

–-

GPIO or SPI slave

out, master in

GPIOF2

SPICLKA (I/O)

33

40

4090.6

42.6

I/O/Z

–

GPIO or SPI clock

GPIOF3

SPISTEA (I/O)

34

41

4185.9

42.6

I/O/Z

–

GPIO or SPI slave

transmit enable

GPIOF OR SCI-A SIGNALS

GPIO or SCI

GPIOF4

SCITXDA (O)

151

170

42.6

2565.1

I/O/Z

PU

asynchronous serial

port TX data

GPIO or SCI

GPIOF5

SCIRXDA (I)

153

172

42.6

2361.3

I/O/Z

PU

asynchronous serial

port RX data

24 IntroductionCopyright © 2009–2010, Texas Instruments Incorporated

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Texas Instruments SM320F2812-HT Signal HFG Center, Gpiod or EVA Signals, Gpiod or EVB Signals, Gpioe or Interrupt Signals

Contents

Data Manual SM320F2812-HT Contents SM320F2812-HT PeripheralsSPI Slave Mode Timing List of Figures General-Purpose Input Timing List of Tables Interrupt Switching Characteristics 149 Copyright 2009-2010, Texas Instruments Incorporated Digital Signal Processor Check for Samples SM320F2812-HTSupports Extreme Temperature Applications Introduction DescriptionHardware Features FeatureDevice Summary F2812Die Layout DIE PAD Backside DIE Size DIE PAD SizeCoordinates Thickness Finish Potential 55.0 x 64.0 μmPin Assignments SM320F2812 172-Pin HFG Cqfp Top ViewSignal Descriptions Signal Descriptions1Center Description HFG Xintf Signals PIN no DIE PADSignal Descriptions Center Description HFGCenter Description HFG Jtag and Miscellaneous Signals Trst TCKTMS TDICenter Description HFG ADC Analog Input Signals Center Description HFG Power Signals Gpiob or EVB Signals SM320F2812-HTPeripheral PIN no DIE PAD Gpio DIE PAD no Signal HFG Center Gpiod or EVA SignalsGpiod or EVB Signals Gpioe or Interrupt SignalsSignal HFG Center Gpiof or can Signals Gpiof or McBSP SignalsGpiof or XF CPU Output Signal Signal HFG Center Gpiog or SCI-B Signals GPIOG4 Scitxdb OGPIOG5 Scirxdb Functional Overview Memory Map F2812 Memory Map See Notes A. Through GAddresses of Flash Sectors in F2812 Address Range Program and Data SpaceWait States AreaComments H0 SaramBrief Descriptions 1 C28x CPUMemory Bus Harvard Bus Architecture Peripheral BusBoot ROM External Interface XintfFlash 7 L0, L1, H0 SARAMsBoot Mode Selection Boot Mode Selected GPIOF4 GPIOF12 GPIOF3 GPIOF2Security Code Security Module DisclaimerLow-Power Modes Peripheral Interrupt Expansion PIE BlockExternal Interrupts XINT1, XINT2, XINT13, Xnmi Oscillator and PLL18 32-Bit CPU Timers 0, 1 Peripheral Frames 0, 1, 2 PFnGeneral-Purpose Input/Output Gpio Multiplexer Control PeripheralsSerial Port Peripherals Register MapAccess Type Peripheral Frame 0 Registers1Peripheral Frame 1 Registers1 Name Address RangePeripheral Frame 2 Registers1 Device Emulation Registers External Interface, XintfDevice Emulation Registers XZCS0XZCS0AND1 XZCS1 XZCS2XZCS6 XZCS6AND7 XZCS7 XWE XRD XR/W Xready XMP/MC Xhold Xholda XclkoutXintf Configuration and Control Register Mappings Timing RegistersXrevision Register Xrevision Register Bit DefinitionsInterrupts INT1 INT2 INT11 INT12 IntmCPU PIE Interrupts 11. PIE Configuration and Control Registers1 External Interrupts 12. External Interrupts RegistersClock and Reset Domains System Control13. PLL, Clocking, Watchdog, and Low-Power Mode Registers1 OSC and PLL Block 14. Pllcr Register Bit DefinitionsPLL Mode Remarks Sysclkout Loss of Input ClockPLL-Based Clock Module External Reference Oscillator Clock OptionWatchdog Block Low-Power Modes Block 16. F2812 Low-Power ModesMode Oscclk Clkin Sysclkout32-Bit CPU-Timers 0/1/2 TddrhtddrPrdhprd Pschpsc TCR.4INT13 PIE TINT1 TINT0 CPU-TIMER INT1 to INT12 C28xINT14 XINT13 TINT2 CPU-Timers 0, 1, 2 Configuration and Control Registers Module and Signal Names for EVA and EVB Event Manager Modules EVA EVB SignalEvent Manager Modules EVA, EVB EVA Registers1 Event Manager a Functional Block Diagram See Note a General-Purpose GP Timers Double Update PWM ModeFull-Compare Units Programmable Deadband GeneratorPWM Characteristics Capture UnitQuadrature-Encoder Pulse QEP Circuit External ADC Start-of-ConversionEnhanced Analog-to-Digital Converter ADC Module Adcenclk Hspclk MUX ADCINA0ADCINA7 ADCADCINA70 ADCINB70Adclo Adcbgrefin ²SM320F2812-HT Adclo AdcbgrefinAvddrefbg Avssrefbg ADC Registers1 Enhanced Controller Area Network eCAN Module Unit SN65HVD23xCan Bus ECAN Memory Map Can Registers Map1 Register Name AddressWhere Clksrg source could be LSPCLK, CLKX, or CLKR.2 Multichannel Buffered Serial Port McBSP ModuleTX Fifo LspclkFSX ClkxName Address Type Reset Value Description McBSP Register SummaryHEX Data REGISTERS, RECEIVE, TransmitFifo Mode Registers applicable only in Fifo mode Serial Communications Interface SCI Module SCI-A Registers1 SCI-B Registers110. Serial Communications Interface SCI Module Block Diagram −−−−−Serial Peripheral Interface SPI Module 10. SPI Registers1 −−−−− −−−−−11. Gpio Mux Registers1 2 Register Description12. Gpio Data Registers1 PIN Device and Development Support Tool Nomenclature Software Development ToolsHardware Development Tools Documentation Support SM320F2812-HT Absolute Maximum Ratings Value UnitElectrical Characteristics Recommended Operating ConditionsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX UnitDie Junction Temperature C HoursMode Test Conditions Current Consumption Graphs VddaioPower Sequencing Requirements Reducing Current ConsumptionPeripheral Module DD Current Reduction mASignal Transition Levels Recommended Low-Dropout RegulatorsSupplier Part Number Timing Parameter Symbology VOH 80% 20% VOLVIH 90% 10% VIL General Notes on Timing Parameters Test Load Circuit85 pF Clock Requirements and Characteristics Device Clock TableInput Clock Requirements Clock Table and NomenclatureOutput Clock Characteristics Xclkin Timing Requirements PLL Bypassed or EnabledXclkin Timing Requirements PLL Disabled1 Possible PLL Configuration Modes1Reset Timing Reset XRS Timing Requirements1XF/XPLLDIS GPIOF14Xclkout XRS XF/XPLLDIS XMP/MCXclkin Xclkout XRS XCLKIN/8GPIOF14/XF XCLKIN/2Low-Power Mode Wakeup Timing 10. Idle Mode Switching Characteristics1A0−A15 Xclkout = Sysclkout11. Standby Mode Switching Characteristics1 Device Status Flushing Pipeline Wake−up Signal StandbyXCLKOUT² Sysclkout Cycles12. Halt Mode Switching Characteristics1 Parameter MIN TYP MAX UnitEvent Manager Interface PWM Timing13. PWM Switching Characteristics1 14. Timer and Capture Unit Timing Requirements1Parameter Test Conditions MIN MAX Unit17. Interrupt Switching Characteristics Interrupt Timing19. General-Purpose Output Switching Characteristics General-Purpose Input/Output Gpio Output Timing18. Interrupt Timing Requirements TxCTRIP, CxTRIP PDPINTx See Note BGeneral-Purpose Input/Output Gpio Input Timing Qualprd SysclkoutQualprd = 1 2 x Sysclkout cycles x Output From Qualifier SPI Master Mode Timing 21. SPI Master Mode External Timing Clock Phase = 01 2GPIOxn Spisimo Spisomi Master In Data Must Be Valid22. SPI Master Mode External Timing Clock Phase = 11 2 SM320F2812-HTData Valid SpisomiSPI Slave Mode Timing 23. SPI Slave Mode External Timing Clock Phase = 01 2SM320F2812-HT 24. SPI Slave Mode External Timing Clock Phase = 11 2 Spisimo Data Must Be ValidSM320F2812-HT 26. Xtiming Register Configuration Restrictions1 External Interface Xintf Timing27. Valid and Invalid Timing1 X2TIMING =28. Xtiming Register Configuration Restrictions1 29. Valid and Invalid Timing when using Synchronous XREADY130. Xtiming Register Configuration Restrictions1 31. Xtiming Register Configuration Restrictions1 33. Xintf Clock ConfigurationsMode Sysclkout Xtimclk Xclkout 32. Asynchronous XREADY128. Relationship Between Xtimclk and Sysclkout XINTCNF2 Clkoff Xtimclk ClkmodeXintf Signal Alignment to Xclkout XR/WExternal Interface Read Timing 35. External Memory Interface Read Timing Requirements1XCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk XZCS0AND1, XZCS2 XZCS6AND7External Interface Write Timing Lead ActiveXCLKOUT=XTIMCLK DoutSM320F2812-HT Setup time, Xready Synch low before Xclkout high/low WS Synch Active Lead Trail DINXREADYSynch WS Asynch XCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk XZCS0AND1, XZCS2XREADYAsynch Parameter MIN MAX Unit 33. Write With Synchronous Xready Access 34. Write With Asynchronous Xready Access Xhold and Xholda XWE, XRD XZCS6AND7 XR/WXHOLD/XHOLDA Timing 44. XHOLD/XHOLDA Timing Requirements Xclkout = XTIMCLK1 2XR/W XZCS0AND1 XZCS2 XZCS6AND7XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 Xtimclk 36. XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 XtimclkOn-Chip Analog-to-Digital Converter ADC Absolute Maximum Ratings46. DC Specifications1 47. AC Specifications1 48. Current Consumption1MIN TYP MAX TYP ADC Operating MODE/CONDITIONSADC Power-Up Control Bit Timing ADCIN0Pwdnbg Pwdnref PwdnadcSequential Sampling Mode Single Channel Smode = Detailed Description50. Sequential Sampling Mode Timing1 Sample n +Clock Remarks Simultaneous Sampling Mode Dual-Channel Smode = AT 25-MHz ADCDefinitions of Specifications and Terminology Multichannel Buffered Serial Port McBSP Timing McBSP Transmit and Receive Timing52. McBSP Timing Requirements1 2 Clkg + Clksrg53. McBSP Switching Characteristics1 2 Dxena =M16 M18 M17 M18M1, M11 M2, M12 M13 M19McBSP as SPI Master or Slave Timing Master Slave Unit MIN MAXParameter Master Slave Unit MIN MAX M39 M49 M58 63. Flash/OTP Access Timing1 Flash TimingRecommended Operating Conditions 62. Flash Parameters at 150-MHz SYSCLKOUT164. Minimum Required Wait-States at Different Frequencies WAIT-STATE Random Wait STATE2250 Mechanical Data Package Type Pins Package Qty Eco Plan Lead Orderable DeviceSamples Page Products Applications DSPRfid