Texas Instruments SM320F2812-HT specifications Signal Descriptions, Center Description HFG

Models: SM320F2812-HT

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SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010www.ti.com

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 2-3. Signal Descriptions (1)

(continued)

 

 

 

 

 

 

 

 

 

 

 

 

PIN NO.

DIE PAD

 

DIE PAD

DIE PAD

I/O/Z (2)

PU/PD (3)

 

 

 

 

 

 

 

 

 

 

 

 

 

NAME

172-PIN

 

X-CENTER

Y-CENTER

 

 

DESCRIPTION

 

 

 

 

 

 

 

 

 

 

 

 

HFG

NO.

 

(μm)

(μm)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Microprocessor/Microcomputer Mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Select. Switches between microprocessor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and microcomputer mode. When high,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Zone 7 is enabled on the external interface.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When low, Zone 7 is disabled from the

 

XMP/MC

 

17

23

 

2308.2

42.6

I

PD

 

external interface and on-chip boot ROM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

may be accessed instead. This signal is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

latched into the XINTCNF2 register on a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

reset and the user can modify this bit in

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

software. The state of the XMP/MC pin is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ignored after reset.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

External Hold Request.

 

 

 

when

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XHOLD,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

active (low), requests the XINTF to release

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the external bus and place all buses and

 

XHOLD

 

 

155

174

 

42.6

2157.6

I

PU

 

strobes into a high-impedance state. The

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XINTF releases the bus when any current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

access is complete and there are no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

pending accesses on the XINTF.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

External Hold Acknowledge.

 

 

 

is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XHOLDA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

driven active (low) when the XINTF has

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

granted a XHOLD request. All XINTF buses

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

and strobe signals are in a high-impedance

 

XHOLDA

80

93

 

5361.5

4137.4

O/Z

 

 

 

 

state. XHOLDA is released when the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XHOLD signal is released. External devices

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

should only drive the external bus when

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XHOLDA is active (low).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XINTF Zone 0 and Zone 1 Chip Select.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XZCS0AND1

is active (low) when an

 

XZCS0AND1

43

50

 

5148.5

42.6

O/Z

 

 

 

 

access to the XINTF Zone 0 or Zone 1 is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

performed.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XINTF Zone 2 Chip Select.

 

 

 

is active

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XZCS2

 

XZCS2

 

 

 

 

86

100

 

5361.5

4844.2

O/Z

 

(low) when an access to the XINTF Zone 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is performed.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XINTF Zone 6 and Zone 7 Chip Select.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XZCS6AND7

is active (low) when an

 

XZCS6AND7

130

146

 

42.6

4888.6

O/Z

 

 

 

access to the XINTF Zone 6 or Zone 7 is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

performed.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Enable. Active-low write strobe. The

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

write strobe waveform is specified, per zone

 

XWE

82

95

 

5361.5

4347.5

O/Z

 

 

 

basis, by the Lead, Active, and Trail periods

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

in the XTIMINGx registers.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Enable. Active-low read strobe. The

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

read strobe waveform is specified, per zone

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

basis, by the Lead, Active, and Trail periods

 

XRD

41

48

 

4900.6

42.6

O/Z

 

 

 

in the XTIMINGx registers.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE: The XRD and XWE signals are

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

mutually exclusive.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Not Write Strobe. Normally held high.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When low, XR/W

indicates write cycle is

 

XR/W

50

57

 

5361.5

755.0

O/Z

 

 

 

active; when high, XR/W indicates read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

cycle is active.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ready Signal. Indicates peripheral is ready

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

to complete the access when asserted to 1.

 

XREADY

157

176

 

42.6

1972.4

I

PU

 

XREADY can be configured to be a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

synchronous or an asynchronous input.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

See the timing diagrams for more details.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Texas Instruments SM320F2812-HT specifications Signal Descriptions, Center Description HFG

SM320F2812-HT specifications

The Texas Instruments SM320F2812-HT is a highly capable digital signal processor (DSP) specifically designed for high-performance and real-time applications in harsh environments. This part of the C2000 family of microcontrollers caters to applications in areas such as industrial automation, motor control, and power conversion, where reliability and durability under extreme temperature conditions are paramount.

One of the standout features of the SM320F2812-HT is its robust architecture based on a 32-bit fixed-point core. This allows for efficient execution of complex algorithms while maintaining a high processing speed. The processor operates at clock speeds of up to 150 MHz, enabling it to handle multiple tasks simultaneously with minimal latency.

The SM320F2812-HT boasts an impressive memory configuration that includes up to 128 KB of flash memory and 4 KB of RAM. The integrated memory supports efficient data handling and storage, making it ideal for demanding applications that require quick access to critical information. The device also features various peripherals, including analog-to-digital converters (ADCs), pulse width modulation (PWM) modules, and serial communication interfaces, which enhance its functionality in real-time processing and control tasks.

Furthermore, this DSP employs advanced control algorithms and supports various communication protocols, allowing it to interoperate seamlessly with other devices within a system. Its capabilities are further enhanced by Texas Instruments’ extensive development tools and software libraries, which enable developers to accelerate design cycles and improve overall efficiency.

With its high temperature rating, the SM320F2812-HT is designed to operate within a temperature range from -40°C to 125°C, making it particularly well-suited for use in automotive, aerospace, and other rugged environments where traditional components might fail. The high reliability and endurance of this microcontroller make it a preferred choice among engineers looking for durable solutions without compromising performance.

In summary, the Texas Instruments SM320F2812-HT represents a powerful blend of processing capabilities, memory architecture, and environmental resilience. Its features make it a go-to option for developers in search of a robust DSP for real-time applications, ensuring that it meets the rigorous demands of various industrial sectors while delivering consistent performance.