Texas Instruments SM320C6455-EP Signal TYPE1 Name, IPD/IPU2 Description Emifa 64 BIT Address

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

Table 2-3. Terminal Functions (continued)

SIGNAL		TYPE(1)
NAME	NO.
AEA19/BOOTMODE3	N25
AEA18/BOOTMODE2	L26
AEA17/BOOTMODE1	L25	O/Z
AEA16/BOOTMODE0	P26
AEA15/AECLKIN_SEL	P27
AEA14/HPI_WIDTH	R25
AEA13/LENDIAN	R27	O/Z
AEA12/UTOPIA_EN	R28

O/Z

AEA11T25

IPD/IPU(2) DESCRIPTION

EMIFA (64 BIT) - ADDRESS

	EMIFA external address (word address) (O/Z)
	Controls initialization of the DSP modes at reset (I) via pullup/pulldown resistors
	[For more detailed information, see Section 3, Device Configuration.]
IPD	Note: If a configuration pin must be routed out from the device and 3-stated
	(not driven), the internal pullup/pulldown (IPU/IPD) resistor should not be relied
	upon; TI recommends the use of an external pullup/pulldown resistor. For more
	detailed information on pullup/pulldown resistors and situations where external
	pullup/pulldown resistors are required, see Section 3.7, Pullup/Pulldown
IPU	Resistors.
	∙ Boot mode - device boot mode configurations (BOOTMODE[3:0]) [Note:
	the peripheral must be enabled to use the particular boot mode.]
	AEA[19:16]:
	0000	- No boot (default mode)
	0001	- Host boot (HPI)
	0010	-Reserved
	0011	- Reserved
	0100	- EMIFA 8 bit ROM boot
	0101	- Master I2C boot
	0110	- Slave I2C boot
	0111	- Host boot (PCI)

1000 thru 1111 - Serial Rapid I/O boot configurations

For more detailed information on the boot modes, see Section 2.4, Boot Sequence.

CFGGP[2:0] pins must be set to 000b during reset for proper operation of the PCI boot mode.

∙ EMIFA input clock source select

Clock mode select for EMIFA (AECLKIN_SEL)

AEA15:

0 - AECLKIN (default mode)

1 - SYSCLK4 (CPU/x) Clock Rate. The SYSCLK4 clock rate is software

	selectable via the Software PLL1 Controller. By default, SYSCLK4 is
	selected as CPU/8 clock rate.
IPD	∙ HPI peripheral bus width (HPI_WIDTH) select
	[Applies only when HPI is enabled; PCI_EN pin = 0]

AEA14:

0 - HPI operates as an HPI16 (default). (HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the Hi-Z state.)

1 - HPI operates as an HPI32.

∙Device Endian mode (LENDIAN) AEA13:

0- System operates in Big Endian mode

1- System operates in Little Endian mode(default)

∙UTOPIA Enable bit (UTOPIA_EN)

AEA12: UTOPIA peripheral enable(functional)

0- UTOPIA disabled; Ethernet MAC (EMAC) and MDIO enable(default). This means all multiplexed EMAC/UTOPIA and MDIO/UTOPIA pins function as EMAC and MDIO. Which EMAC/MDIO configuration (interface) [MII, RMII, GMII or the standalone RGMII] is controlled by the MACSEL[1:0] bits.

1- UTOPIA enabled; EMAC and MDIO disabled [except when the MACSEL[1:0] bits = 11 then, the EMAC/MDIO RGMII interface is still functional].

This means all multiplexed EMAC/UTOPIA and MDIO/UTOPIA pins now function as UTOPIA. And if MACSEL[1:0] = 11, the RGMII standalone pin functions can be used.

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