SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.22.3IEEE 1149.1 JTAG

7.22.3.1JTAG Device-Specific Information

7.22.3.1.1IEEE 1149.1 JTAG Compatibility Statement

For maximum reliability, the C6455 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.

7.22.4JTAG Peripheral Register Description(s)

7.22.5JTAG Electrical Data/Timing

Table 7-116. Timing Requirements for JTAG Test Port (see Figure 7-79)

 

 

 

-720

 

 

 

 

 

-850

 

 

NO.

 

 

A-1000/-1000

UNIT

 

 

 

-1200

 

 

 

 

 

MIN

MAX

 

1

tc(TCK)

Cycle time, TCK

35

 

ns

3

tsu(TDIV-TCKH)

Setup time, TDI/TMS/TRST valid before TCK high

10

 

ns

4

th(TCKH-TDIV)

Hold time, TDI/TMS/TRST valid after TCK high

9

 

ns

Table 7-117. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port

(see Figure 7-79)

 

 

 

-720

 

 

 

 

 

-850

 

 

NO.

PARAMETER

A-1000/-1000

UNIT

 

 

 

-1200

 

 

 

 

 

MIN

MAX

 

2

td(TCKL-TDOV)

Delay time, TCK low to TDO valid

-3

18

ns

 

 

1

 

 

 

 

TCK

 

 

 

 

 

 

2

2

 

 

 

TDO

 

 

 

 

 

 

3

4

 

 

 

 

 

 

 

 

TDI/TMS/TRST

 

 

 

 

 

 

Figure 7-79. JTAG Test-Port Timing

 

 

 

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C64x+ Peripheral Information and Electrical Specifications

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Texas Instruments SM320C6455-EP manual Ieee 1149.1 Jtag, Jtag Device-Specific Information, Delay time, TCK low to TDO valid