Texas Instruments SM320C6455-EP manual Emifa 64 BIT Control Signals Common to ALL Types of Memory

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

	Table 2-3. Terminal Functions	(continued)
SIGNAL	TYPE(1) IPD/IPU(2)	DESCRIPTION
NAME
	NO.

EMIFA (64 BIT) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY

ABA1/EMIFA_EN V25 O/Z IPD

ABA0/DDR2_EN V26 O/Z IPD

ACE5	V27	O/Z	IPU
ACE4	V28	O/Z	IPU
ACE3	W26	O/Z	IPU
ACE2	W27	O/Z	IPU
ABE7	W29	O/Z	IPU
ABE6	K26	O/Z	IPU
ABE5	L29	O/Z	IPU
ABE4	L28	O/Z	IPU
ABE3	AA29	O/Z	IPU
ABE2	AA28	O/Z	IPU
ABE1	AA25	O/Z	IPU
ABE0	AA26	O/Z	IPU

EMIFA bank address control (ABA[1:0])

∙Active-low bank selects for the 64 bit EMIFA.

When interfacing to 16 bit Asynchronous devices, ABA1 carries bit 1 of the byte address.

For an 8 bit Asynchronous interface, ABA[1:0] are used to carry bits 1 and 0 of the byte address

DDR2 Memory Controller enable (DDR2_EN) [ABA0]

0 - DDR2 Memory Controller peripheral pins are disabled (default) 1 - DDR2 Memory Controller peripheral pins are enabled

EMIFA enable (EMIFA_EN) [ABA1]

0 - EMIFA peripheral pins are disabled (default)

1 - EMIFA peripheral pins are enabled

EMIFA memory space enables

∙ Enabled by bits 28 through 31 of the word address

∙ Only one pin is asserted during any external data access Note: The C6455 device does not have ACE0 and ACE1 pins

EMIFA byte-enable control

∙ Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory.

∙ Byte-write enables for most types of memory.

			EMIFA (64 BIT) - BUS ARBITRATION
AHOLDA	N26	O	IPU	EMIFA hold-request-acknowledge to the host
AHOLD	R29	I	IPU	EMIFA hold request from the host
ABUSREQ	L27	O	IPU	EMIFA bus request output
	EMIFA (64 BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
				EMIFA external input clock. The EMIFA input clock (AECLKIN or SYSCLK4
AECLKIN	N29	I	IPD	clock) is selected at reset via the pullup/pulldown resistor on the AEA[15] pin.
				Note: AECLKIN is the default for the EMIFA input clock.
AECLKOUT	V29	O/Z	IPD	EMIFA output clock [at EMIFA input clock (AECLKIN or SYSCLK4) frequency]
AAWE/ASWE	AB25	O/Z	IPU	Asynchronous memory write-enable/Programmable synchronous interface
				write-enable
AARDY	K29	I	IPU	Asynchronous memory ready input
AR/W	W25	O/Z	IPU	Asynchronous memory read/write
AAOE/ASOE	Y28	O/Z	IPU	Asynchronous/Programmable synchronous memory output-enable
				Programmable synchronous address strobe or read-enable
				∙ For programmable synchronous interface, the R_ENABLE field in the Chip
ASADS/ASRE	R26	O/Z	IPU	Select x Configuration Register selects between ASADS and ASRE:
				– If R_ENABLE = 0, then the ASADS/ASRE signal functions as the
				ASADS signal.

– If R_ENABLE = 1, then the ASADS/ASRE signal functions as the ASRE signal.

Submit Documentation Feedback Device Overview 33