Texas Instruments SM320C6455-EP manual Parameter Information, 1 3.3-V Signal Transition Levels

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7 C64x+ Peripheral Information and Electrical Specifications

7.1Parameter Information

42Ω

4.0pF

3.5nH

1.85pF

Tester Pin Electronics

Transmission Line

Z0 = 50 Ω

(see Note)

Data Sheet Timing Reference Point

Output

Under

Test

Device Pin

(see Note)

NOTE: This data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.

Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.

Figure 7-1. Test Load Circuit for AC Timing Measurements

The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving.

7.1.13.3-V Signal Transition Levels

All input and output timing parameters are referenced to 1.5 V for both "0" and "1" logic levels.

Vref = 1.5 V

Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements

All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOLMAX and VOH MIN for output clocks.

Vref = VIH MIN (or VOH MIN)

Vref = VIL MAX (or VOL MAX)

Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels

7.1.23.3-V Signal Transition Rates

All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).

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