Texas Instruments SM320C6455-EP manual Signal TYPE1 IPD/IPU2 Description Name

SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR					www.ti.com
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
		Table 2-3. Terminal Functions			(continued)
SIGNAL		TYPE(1)	IPD/IPU(2)		DESCRIPTION
NAME	NO.
MULTICHANNEL BUFFERED SERIAL PORT 1 AND MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP1 and McBSP0)
CLKS	AJ4	I	IPD	McBSP external clock source (as opposed to internal) (I)
				[shared by McBSP1 and McBSP0]
		MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKR1/GP[0]	AF4	I/O/Z	IPD	McBSP1 receive clock (I/O/Z) or GP[0] (I/O/Z) [default]
FSR1/GP[10]	AE5	I/O/Z	IPD	McBSP1 receive frame sync (I/O/Z) or GP[10] (I/O/Z)[default]
DR1/GP[8]	AH5	I/O/Z	IPD	McBSP1 receive data (I) or GP[8] (I/O/Z) [default]
DX1/GP[9]	AG5	I/O/Z	IPD	McBSP1 transmit data (O/Z) or GP[9] (I/O/Z) [default]
FSX1/GP[11]	AG4	I/O/Z	IPD	McBSP1 transmit frame sync (I/O/Z) or GP[11] (I/O/Z) [default]
CLKX1/GP[3]	AF5	I/O/Z	IPD	McBSP1 transmit clock (I/O/Z) or GP[3] (I/O/Z) [default]
		MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKR0	AG1	I/O/Z	IPU	McBSP0 receive clock (I/O/Z)
FSR0	AH3	I/O/Z	IPD	McBSP0 receive frame sync (I/O/Z)
DR0	AJ5	I	IPD	McBSP0 receive data (I)
DX0	AF6	I/O/Z	IPD	McBSP0 transmit data (O/Z)
FSX0	AJ3	I/O/Z	IPD	McBSP0 transmit frame sync (I/O/Z)
CLKX0	AG6	I/O/Z	IPU	McBSP0 transmit clock (I/O/Z)

UNIVERSAL TEST AND OPERATIONS PHY INTERFACE for ASYNCHRONOUS TRANSFER MODE (ATM) [UTOPIA SLAVE]

UTOPIA SLAVE (ATM CONTROLLER) - TRANSMIT INTERFACE

UXCLK/MTCLK/

Source clock for UTOPIA transmit driven by Master ATM Controller.

When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this

RMREFCLK

N4 I/O/Z

pin is either EMAC MII transmit clock (MTCLK) or the EMAC RMII reference clock. The EMAC function is controlled by the MACSEL[1:0] (AEA[10:9] pins). For more detailed information, see Section 3, Device Configuration.

Transmit cell available status output signal from UTOPIA Slave.

UXCLAV/GMTCLK K5 I/O/Z

UXENB/MTXEN/

0 indicates a complete cell is NOT available for transmit 1 indicates a complete cell is available for transmit

When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is EMAC GMII transmit clock. MACSEL[1:0] dependent.

UTOPIA transmit interface enable input signal. Asserted by the Master ATM Controller to indicate that the UTOPIA Slave should put out on the Transmit Data Bus the first byte of valid data and the UXSOC signal in the next clock

RMTXEN

J5 I/O/Z

cycle.

When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is either the EMAC MII transmit enable [default] or EMAC RMII transmit enable or EMAC GMII transmit enable. MACSEL[1:0] dependent.

UXSOC/MCOL	K3	I/O/Z
UXADDR4/MDCLK	M5	I
UXADDR3/MDIO	N3	I
UXADDR2/PCBE3	P5	I
UXADDR1/PIDSEL	R3	I
UXADDR0/PTRDY	P4	I

Transmit Start-of-Cell signal. This signal is output by the UTOPIA Slave on the rising edge of the UXCLK, indicating that the first valid byte of the cell is available on the 8 bit Transmit Data Bus (UXDATA[7:0]).

When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this pin is either the EMAC MII collision sense or EMAC GMII collision sense. MACSEL[1:0] dependent.

UTOPIA transmit address pins (UXADDR[4:0]) (I)

As UTOPIA transmit address pins, UTOPIA_EN (AEA12 pin) = 1:

∙5 bit Slave transmit address input pins driven by the Master ATM Controller to identify and select one of the Slave devices (up to 31 possible) in the

ATM System.

When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0) and if the PCI_EN pin = 1, these pins are PCI peripheral pins:

PCI command/byte enable 3(PCBE3) [I/O/Z], PCI initialization device select (PIDSEL) [I], and PCI target ready (PTRDY) [I/O/Z].

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