URADDR2/PINTA1/ GP14 URADDR1/PRST | Texas Instruments SM320C6455-EP

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

Table 2-3. Terminal Functions (continued)

SIGNAL

NAME

UXDATA7/MTXD7

UXDATA6/MTXD6

UXDATA5/MTXD5

UXDATA4/MTXD4 UXDATA3/MTXD3 UXDATA2/MTXD2

UXDATA1/MTXD1/

RMTXD1

UXDATA0/MTXD0/

RMTXD0

URCLK/MRCLK

URCLAV/MCRS/ RMCRSDV

URENB/MRXDV

URSOC/MRXER/ RMRXER

URADDR4/PCBE0/

GP[2]

URADDR3/PREQ/

GP[15]

URADDR2/PINTA(1)/ GP[14]

URADDR1/PRST/

GP[13]

URADDR0/PGNT/

GP[12]

URDATA7/MRXD7 URDATA6/MRXD6 URDATA5/MRXD5

URDATA4/MRXD4 URDATA3/MRXD3 URDATA2/MRXD2

URDATA1/MRXD1/

RMRXD1

URDATA0/MRXD0/

RMRXD0

NO.

TYPE(1) IPD/IPU(2)	DESCRIPTION
	UTOPIA 8 bit transmit data bus (I/O/Z) [default] or EMAC MII 4 bit transmit data
	bus (I/O/Z) [default] or EMAC GMII 8 bit transmit data bus or EMAC RMII 2 bit
	transmit data bus (I/O/Z)
	Using the Transmit Data Bus, the UTOPIA Slave (on the rising edge of the
O/Z	UXCLK) transmits the 8 bit ATM cells to the Master ATM Controller.
	When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these
	pins function as EMAC pins and are controlled by the MACSEL[1:0] (AEA[10:9]
	pins) to select the MII, RMII, GMII or RGMII EMAC interface. (For more details,
	see Section 3, Device Configuration).

UTOPIA SLAVE (ATM CONTROLLER) - RECEIVE INTERFACE

		Source clock for UTOPIA receive driven by Master ATM Controller.
	I/O/Z	When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
		pin is EMAC MII [default] or GMII receive clock. MACSEL[1:0] dependent.
		Receive cell available status output signal from UTOPIA Slave.
		0 indicates NO space is available to receive a cell from Master ATM Controller
	I/O/Z	1 indicates space is available to receive a cell from Master ATM Controller
	I/O/Z	When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this

		pin is EMAC MII carrier sense [default] or RMII carrier sense/data valid or GMII
		carrier sense. MACSEL[1:0] dependent. MACSEL[1:0] dependent.
		UTOPIA receive interface enable input signal. Asserted by the Master ATM
		Controller to indicate to the UTOPIA Slave to sample the Receive Data Bus
	I/O/Z	(URDATA[7:0]) and URSOC signal in the next clock cycle or thereafter.
		When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this
		pin is EMAC MII [default] or GMII receive data valid. MACSEL[1:0] dependent.
		Receive Start-of-Cell signal. This signal is output by the Master ATM Controller
		to indicate to the UTOPIA Slave that the first valid byte of the cell is available to
	I/O/Z	sample on the 8 bit Receive Data Bus (URDATA[7:0]).
	I/O/Z	When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), this

		pin is EMAC MII [default] or RMII or GMII receive error. MACSEL[1:0]
		dependent.
	I	UTOPIA receive address pins [URADDR[4:0] (I)]:
	I	As UTOPIA receive address pins, UTOPIA_EN (AEA12 pin) = 1:
		As UTOPIA receive address pins, UTOPIA_EN (AEA12 pin) = 1:
	I	∙ 5 bit Slave receive address input pins driven by the Master ATM Controller
	I	to identify and select one of the Slave devices (up to 31 possible) in the
	I	ATM System.
	I	∙ When the UTOPIA peripheral is disabled [UTOPIA_EN (AEA12 pin) = 0],
		these pins are PCI (if PCI_EN = 1) or GPIO (if PCI_EN = 0) pins
	I	(GP[15:12, 2]).
	I

As PCI peripheral pins:

PCI command/byte enable 0 (PCBE0) [I/O/Z]

PCI bus request (PREQ) [O/Z],

IPCI interrupt A (PINTA) [O/Z], PCI reset (PRST) [I], and PCI bus grant (PGNT) [I/O/Z].

UTOPIA 8 bit Receive Data Bus (I/O/Z) [default] or EMAC receive data bus [MII] [default] (I/O/Z) or [GMII] (I/O/Z) or [RMII] (I/O/Z)

Using the Receive Data Bus, the UTOPIA Slave (on the rising edge of the

URCLK) can receive the 8 bit ATM cell data from the Master ATM Controller.

I/O/Z

When the UTOPIA peripheral is disabled (UTOPIA_EN [AEA12 pin] = 0), these pins function as EMAC pins and are controlled by the MACSEL[1:0] (AEA[10:9] pins) to select the MII, RMII, GMII, or RGMII EMAC interface. (For more details, see Section 3, Device Configuration).

(1)These pins function as open-drain outputs when configured as PCI pins.

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Device Overview

Texas Instruments SM320C6455-EP URADDR2/PINTA1/ GP14 URADDR1/PRST, TYPE1 IPD/IPU2 Description

Models: SM320C6455-EP