SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.14.4.3 MDIO Electrical Data/Timing

Table 7-90. Timing Requirements for MDIO Input (R)(G)MII (see Figure 7-71)

NO.

1 tc(MDCLK)

2a tw(MDCLK)

2b tw(MDCLK)

3 tt(MDCLK)

4tsu(MDIO-MDCLKH)

5th(MDCLKH-MDIO)

 

-720

 

 

 

-850

 

 

 

A-1000/-1000

UNIT

 

-1200

 

 

 

MIN

MAX

 

Cycle time, MDCLK

400

 

ns

Pulse duration, MDCLK high

180

 

ns

Pulse duration, MDCLK low

180

 

ns

Transition time, MDCLK

 

5

ns

Setup time, MDIO data input valid before MDCLK high

10

 

ns

Hold time, MDIO data input valid after MDCLK high

10

 

ns

1

MDCLK

3

4

MDIO (input)

Figure 7-71. MDIO Input Timing

Table 7-91. Switching Characteristics Over Recommended Operating Conditions for MDIO Output

(see Figure 7-72)

 

 

 

-720

 

 

 

 

 

-850

 

 

NO.

 

PARAMETER

A-1000/-1000

UNIT

 

 

 

-1200

 

 

 

 

 

MIN

MAX

 

7

td(MDCLKL-MDIO)

Delay time, MDCLK low to MDIO data output valid

 

100

ns

1

MDCLK

7

MDIO (output)

Figure 7-72. MDIO Output Timing

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Texas Instruments SM320C6455-EP manual Mdio input, Delay time, Mdclk low to Mdio data output valid 100, Mdio output