Texas Instruments SM320C6455-EP manual McBSP Electrical Data/Timing, 720 850 1000/-1000

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.13.2McBSP Electrical Data/Timing

7.13.2.1Multichannel Buffered Serial Port (McBSP) Timing

Table 7-59. Timing Requirements for McBSP(1) (see Figure 7-52)

NO.

2 tc(CKRX)

3 tw(CKRX)

5tsu(FRH-CKRL)

6th(CKRL-FRH)

7tsu(DRV-CKRL)

8th(CKRL-DRV)

10tsu(FXH-CKXL)

11th(CKXL-FXH)

		-720
		-850
		A-1000/-1000	UNIT
		-1200
		MIN	MAX
Cycle time, CLKR/X	CLKR/X ext	6P or 10(2)(3)	ns
Pulse duration, CLKR/X high or CLKR/X low	CLKR/X ext	0.5tc(CKRX) –1(4)	ns
Setup time, external FSR high before CLKR low	CLKR int	9	ns
	CLKR ext	1.3
Hold time, external FSR high after CLKR low	CLKR int	6	ns
	CLKR ext	3
Setup time, DR valid before CLKR low	CLKR int	8	ns
	CLKR ext	0.9
Hold time, DR valid after CLKR low	CLKR int	3	ns
	CLKR ext	3.1
Setup time, external FSX high before CLKX low	CLKX int	9	ns
	CLKX ext	1.3
Hold time, external FSX high after CLKX low	CLKX int	6	ns
	CLKX ext	3

(1)CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2)P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(3)Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.

(4)This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP(1)(2)

(see Figure 7-52)

NO.

1td(CKSH-CKRXH)

2 tc(CKRX)

PARAMETER

Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from CLKS input(3)

Cycle time, CLKR/X CLKR/X int

-720
-850
A-1000/-1000		UNIT
-1200
MIN	MAX
1.4	10	ns
6P or 10(4)(5)(6)		ns

(1)CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2)Minimum delay times also represent minimum output hold times.

(3)The CLKS signal is shared by both McBSP0 and McBSP1 on this device.

(4)Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.

(5)P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(6)Use whichever value is greater.

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