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Texas Instruments SM320C6455-EP manual PLL Controller Divider 5 Register, D5EN

Models: SM320C6455-EP

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SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.7.3.5 PLL Controller Divider 5 Register

The PLL controller divider 5 register (PLLDIV5) is shown in Figure 7-15and described in Table 7-23.

31					16
			Reserved
			R-0
15	14		5	4	0
D5EN			Reserved		RATIO
R/W-1			R-0		R/W-3
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
	Figure 7-15. PLL Controller Divider 5 Register (PLLDIV5) [Hex Address: 029A 0164]
		Table 7-23. PLL Controller Divider 5 Register (PLLDIV5) Field Descriptions
Bit	Field	Value	Description
31:16	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
15	Dn4EN		Divider 4 enable bit.
		0	Divider 4 is disabled. No clock output.
		1	Divider 4 is enabled.
14:5	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
4:0	RATIO	0-1Fh	Divider ratio bits.
		0	÷1. Divide frequency by 1.
		1h	÷2. Divide frequency by 2.
		2h	÷3. Divide frequency by 3.
		3h	÷4. Divide frequency by 4.
		4h-7h	÷5 to ÷8. Divide frequency by 5 to divide frequency by 8.
		8h-1Fh	Reserved, do not use.

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C64x+ Peripheral Information and Electrical Specifications

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Texas Instruments SM320C6455-EP manual PLL Controller Divider 5 Register, D5EN

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Data Manual Data Manual FIXED-POINT Digital Signal Processor C64x+ Peripheral Information and Electrical Specifications Recommended Operating ConditionsFIXED-POINT Digital Signal Processor Enhanced Turbo Decoder Coprocessor TCP2 Features ZTZ/GTZ BGA Package Bottom View DescriptionZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View Submit Documentation Feedback Functional Block Diagram Functional Block DiagramDevice Characteristics Characteristics of the C6455 ProcessorHardware Features C6455CPU DSP Core Description FIXED-POINT Digital Signal Processor C64x+ CPU DSP Core Data Paths Memory Map Summary C6455 Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range 02CF Ffff 02DF Ffff03FF Ffff 0FFF FfffBoot Sequence Boot Modes SupportedFIXED-POINT Digital Signal Processor 2 2nd-Level Bootloaders Pin Assignments Pin MapC6455 Pin Map Bottom View Quadrant B C6455 Pin Map Bottom View Quadrant C C6455 Pin Map Bottom View Quadrant D Signal Groups Description TINPL1 TOUTL1 TINPL0Gpio URADDR4/PCBE0/GP2C SYSCLK4/GP1AACE5A ACE4A ACE3AACE2A ABE7 ABE6 ABE5 ABE4HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 only HpiaCLKR1/GP0 Clks SharedUXADDR3/MDIO RgmdioUXADDR4/MDCLK URSOC/MRXER/RMRXERUXDATA4/MTXD4 URDATA3/MRXD3 UXDATA3/MTXD3 URDATA2/MRXD2 UXDATA2/MTXD2UXDATA1/MTXD1/RMTXD1 UXDATA0/MTXD0/RMTXD0Signal IPD/IPU Description Name CLOCK/PLL ConfigurationsTerminal Functions Terminal FunctionsSignal Name Type 1 IPD/IPU Emifa 64 BIT Control Signals Common to ALL Types of Memory Emifa 64 BIT BUS ArbitrationEmifa 64 BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control Signal TYPE1 Name IPD/IPU2 Description Emifa 64 BIT AddressAEA1916 AEA15IPD/IPU Description Name AEA6AEA5 AEA4Signal TYPE1 IPD/IPU2 Description Name Emifa 64 BIT Data AED21 AED20AED19 AED18IPD/IPU2 Description DDR2 Memory Controller 32 BIT AddressTimer IPD/IPU Description Name DDR2 Memory Controller 32 BIT DataINTER-INTEGRATED Circuit I2C Signal TYPE1 IPD/IPU2 Description Name Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 Utopia Slave ATM Controller Transmit InterfaceURADDR2/PINTA1/ GP14 URADDR1/PRST TYPE1 IPD/IPU2 DescriptionUtopia Slave ATM Controller Receive Interface Signal TYPE1 IPD/IPU2 Description Name Rapidio Serial Port Management Data INPUT/OUTPUT Mdio for MII/RMII/GMIIManagement Data INPUT/OUTPUT Mdio for Rgmii Device Configuration Rgrefclk RSV05RSV07 RSV09 Reserved for TestRSV13 RSV14RSV15 RSV16Signal TYPE1 Name no IPD/IPU2 Description Supply Voltage Monitor PinsSupply Voltage Pins U16 AA1 AA6 AB7AC6 AC9 AD5 AD7 AE6 AE8AF1 CV DDGround Pins CvddGND F20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AA2 AA7 AB6AC7 AC8 AD6 AE4 AE7GND AF2 AH1Development Development SupportDevice Support Device and Development-Support Tool NomenclatureSM=Qualifieddevice C6000 DSP platforms FIXED-POINT Digital Signal Processor Device Configuration at Device Reset C6455 Device Configuration Pins AEA190, ABA10, and PcienConfiguration IPD PIN IPU1AEA14 AEA13AEA12 AEA11Peripheral Configuration at Device Reset Configuration IPD Functional Description PINIPU ABA0Configuration PIN Setting Utopiaen Pcien PIN UTOPIAEN, and MACSEL10 Peripheral Selection Utopia and EmacLower Upper AUTO-INITPeripheral Selection After Device Reset Peripheral StatesState Peripherals That can be This StateStatic Powerdown Reset Enable Progress Disabled Enabled Unlock the PERCFG0 register by Using the Perlock registerDevice State Control Registers Device State Control RegistersHEX Address Range Acronym Register Name Peripheral Lock Register Description LockvalBit Field Value Description 310 LockvalPeripheral Configuration Register 0 Description Bit Field Value DescriptionBit Field Peripheral Configuration Register 1 Description DDR2CTL EmifactlDDR2CTL Peripheral Status Registers Description HpistatI2CSTAT 1715 SM320C6455-EP Utopiastat PcistatUtopiastat Emac Configuration Register Emaccfg Description RmiirstEmulator Buffer Powerdown Register Emubufpd Description EmuctlDevice Status Register Description Emifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0Sysclkout MCBSP1EN PCI66 Pcieeai MACSEL1 MACSEL0Pcieeai MACSEL10Utopiaen BOOTMODE30 Jtag ID Jtagid Register DescriptionVariant Part Number Manufacturer LSB VariantConfiguration Examples Pullup/Pulldown ResistorsHPI VCP2 HRDY,HINT FIXED-POINT Digital Signal Processor Internal Buses, Bridges, and Switch Fabrics System InterconnectData Switch Fabric Connections Switched Central Resource Block Diagram Configuration Switch Fabric SCR Connection MatrixC64x+ Megamodule SCR Connection C6455 Default Bus Master Priorities BUS Master Default Priority Control Priority LevelBus Priorities X+ Megamodule Block Diagram Memory ArchitectureC6455 L1P Memory Configurations C6455 L2 Memory Configurations Memory Protection Bandwidth ManagementAvailable Memory Page Protection Schemes AID0 BitPower-Down Control Megamodule ResetsMegamodule Reset Global or Local Reset Type MegamoduleMegamodule Revision Version Revision aVersion RevisionC64x+ Megamodule Register Descriptions Megamodule Interrupt RegistersMegamodule Powerdown Control Registers Megamodule Revision RegisterMegamodule Idma Registers Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA4 L2MPPA5L2MPPA6 L2MPPA7L1PMPPA18 L1PMPPA19L1PMPPA20 L1PMPPA2111. Device Configuration Registers Chip-Level Registers 10. CPU Megamodule Bandwidth Management RegistersHEX Address Range Acronym Register Name Comments Recommended Operating Conditions DV DD12, DV DDRM, AV DDT, AV DDAMIN NOM MAX Unit AV DDARecommended Operating Conditions VSS VIH VILVOS Parameter Test CONDITIONS1 MIN TYP MAX Unit VOH VOLTDO DVDD33 = MIN IOH = MAX DVDD33 = MIN IOL = MAXCurrent DC 1 3.3-V Signal Transition Levels 2 3.3-V Signal Transition RatesParameter Information Timing Parameters and Board Routing Analysis Recommended Clock and Control Signal Transition Behavior Power SuppliesPower-Supply Sequencing Power-Supply Decoupling108 Enhanced Direct Memory Access EDMA3 Controller EDMA3 Device-Specific Information EDMA3 Channel Synchronization EventsC6455 EDMA3 Channel Synchronization Events1 Edma Binary Event Name Event Description ChannelEDMA3 Peripheral Register Descriptions C6455 EDMA3 Channel Synchronization EventsEDMA3 Channel Controller Registers DCHMAP8 DCHMAP9DCHMAP10 DCHMAP11DCHMAP55 DCHMAP56DCHMAP57 DCHMAP58DRAE5 DRAEH5DRAE6 DRAEH6QSTAT0 QSTAT1QSTAT2 QSTAT3Shadow Region 0 Channel Registers Interrupt Enable Register High EDMA3 Parameter RAM1 EDMA3 Transfer Controller 0 RegistersEDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 121 EDMA3 Transfer Controller 3 Registers 123 Interrupts Interrupt Sources and Interrupt Controller10. C6455 System Event Mapping Event Number Interrupt Event DescriptionXINT0 RINT1XINT1 TINTLO0L1PED1 PdcintL1PCMPA L1PDMPAExternal Interrupts Electrical Data/Timing 11. Timing Requirements for External Interrupts1 see FigureNMI Reset Controller Power-on Reset POR Pin12. Reset Types Type InitiatorWarm Reset Reset Pin Max Reset System ResetCPU Reset Reset Priority Reset Controller Register Reset Type Status Register DescriptionSrst Mrst Wrst POR SrstReset Electrical Data/Timing 14. Timing Requirements for Reset12 3see -8and Figure720 1000/-1000 Unit ParameterPower-Up Timing Resetstat CLKIN1 CLKIN2 PORPLL1 and PLL1 Controller 1 PLL1 Controller Device-Specific Information Internal Clocks and Maximum Operating Frequencies1.3 PLL1 Stabilization, Lock, and Reset Times Clock Signal MIN MAX Unit16. PLL1 Clock Frequency Ranges 1.2 PLL1 Controller Operating Modes17. PLL1 Stabilization, Lock, and Reset Times 18. PLL1 Controller Registers Including Reset Controller2 PLL1 Controller Memory Map MIN TYP3 PLL1 Controller Register Descriptions 3.1 PLL1 Control RegisterPllrst PllpwrdnPLL Multiplier Control Register 20. PLL Multiplier Control Register Pllm Field DescriptionsPLL Pre-Divider Control Register PredenRatio PLL Controller Divider 4 Register D4ENPLL Controller Divider 5 Register D5ENPLL Controller Command Register GosetPLL Controller Status Register GostatPLL Controller Clock Align Control Register Plldiv Ratio Change Status Register SYS5 SYS4SYS5 Sysclk Status Register SYS5ON SYS4ON SYS3ON SYS2ON29. Timing Requirements for CLKIN1 Devices123 see Figure PLL ModesSYSCLK4 23. PLL2 Block Diagram PLL2 and PLL2 Controller1 PLL2 Controller Device-Specific Information 31. PLL2 Clock Frequency Ranges1.2 PLL2 Controller Operating Modes Pllref Pllen =2 PLL2 Controller Memory Map 3 PLL2 Controller Register Descriptions32. PLL2 Controller Registers HEX Address Range Acronym DescriptionPLL Controller Divider 1 Register D1EN155 ALN1 SYS1 SYS1ON 4 PLL2 Controller Input Clock Electrical Data/Timing 39. Timing Requirements for CLKIN2123 see FigureDDR2 Memory Controller 1 DDR2 Memory Controller Device-Specific Information2 DDR2 Memory Controller Peripheral Register Descriptions 3 DDR2 Memory Controller Electrical Data/Timing40. DDR2 Memory Controller Registers External Memory Interface a Emifa Emifa Device-Specific InformationEmifa Peripheral Register Descriptions 41. Emifa RegistersEmifa Electrical Data/Timing 42. Timing Requirements for Aeclkin for EMIFA12 see FigureAeclkin See -33and Figure Aeclkin AECLKOUT1Setup = Hold = ACEx ABE70ABA10 AED630 Read Data AAOE/ASOE a AAWE/ASWE a AR/W Aardy B DeassertedStrobe Setup = Extended Strobe ABA10 AED630Aeclkout Aardya Asserted Deasserted Setup time, read AEDx valid before Aeclkout high SM320C6455-EP BE1 BE2 BE3 BE4EA1 EA2 EA3 EA4 ASADS/ASRE B AAOE/ASOE B AAWE/ASWEBWrite Latency = HOLD/HOLDA Timing HHOLDAL-HOLDL Hold time, Hold low after Holda lowDSP Owns Bus Hold HoldaDelay time, Aeclkout high to Abusreq valid AECLKOUTx Busreq Timing11 I2C Peripheral 11.1 I2C Device-Specific InformationI2COAR I2CCLKH I2CSARI2CXSR I2CEMDR11.2 I2C Peripheral Register Descriptions 51. I2C RegistersStandard Mode Fast Mode MIN MAX 11.3 I2C Electrical Data/TimingSDA SCL Stop StartStart Stop 43. I2C Transmit Timings Stop Start RepeatedHost-Port Interface HPI Peripheral HPI Device-Specific InformationHPI Peripheral Register Descriptions 54. HPI Control RegistersHPI Electrical Data/Timing See -56through Figure NO.PARAMETERHCS Has HCNTL10HR/W Hhwil Hstrobea HD150HR/W Hhwil Hstrobe a Hrdyb46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used 48. HPI32 Read Timing has Not Used, Tied High 49. HPI32 Read Timing has Used Has input HCNTL10 Input HR/W input Input HCS input51. HPI32 Write Timing has Used Input HCS input HD310 inputMultichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers McBSP Electrical Data/Timing 720 850 1000/-1000FIXED-POINT Digital Signal Processor Clks Clkr ClkxClks Master Slave MIN MAX MASTER3 Slave MIN MAXClkx FSX Bit Bitn-1Setup time, DR valid before Clkx high 18P Master Slave MINHold time, DR valid after Clkx high + 36P 198 199 Ethernet MAC Emac Ethernet BusEmac Device-Specific Information Interface Modes70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii Modes Ball Number Device PIN NameRmii Interface Mode Clocking Emac Peripheral Register Descriptions 71. Ethernet MAC Emac Control RegistersMacconfig SoftresetRX6FREEBUFFER RX7FREEBUFFER72. Emac Statistics Registers HEX Address Range Acronym73. Emac Control Module Registers 74. Emac Descriptor Memory02C8 2000 02C8 3FFF Emac Descriptor Memory Emac Electrical Data/Timing Mbps Gmii OnlyMrclk Input MtclkGmtclk OutputMrclk Input MRXD7−MRXD4GMII only MRXD3−MRXD0Mtclk Input MTXD7−MTXD4GMII only MTXD3−MTXD0Mtxen Outputs Gmtclk OutputEmac Rmii Electrical Data/Timing Rmrefclk InputMRXD1-MRXD0 Mcrsdv Mrxer Inputs 720 1000/-1000 UnitEmac Rgmii Electrical Data/Timing Cycle time, TXC Mbps 40*t cTXC 60*t cTXC 70. Emac Transmit Interface Timing Rgmii OperationAB Management Data Input/Output Mdio Mdio Device-Specific InformationMdio Peripheral Register Descriptions 89. Mdio Registers Delay time, Mdclk low to Mdio data output valid 100 MdclkMdio input Mdio outputTimers Timers Device-Specific InformationTimers Peripheral Register Descriptions 92. Timer 0 RegistersTimers Electrical Data/Timing 94. Timing Requirements for Timer Inputs1 see FigureTINPLx TOUTLx Enhanced Viterbi-Decoder Coprocessor VCP2 16.1 VCP2 Device-Specific Information16.2 VCP2 Peripheral Register Descriptions 96. VCP2 RegistersEnhanced Turbo Decoder Coprocessor TCP2 17.1 TCP2 Device-Specific InformationTbhd Tbsd17.2 TCP2 Peripheral Register Descriptions 97. TCP2 Registers98. Default Values for PCI Configuration Registers Register Default ValuePeripheral Component Interconnect PCI PCI Device-Specific Information99. PCI Configuration Registers PCI Peripheral Register Descriptions100. PCI Back End Configuration Registers 101. DSP-toPCI Address Translation Registers 102. PCI Hook Configuration Registers 103. PCI External Memory SpaceHEX Address Offset Acronym Register Name 48FF Ffff 49FF Ffff4A7F Ffff 4AFF FfffPCI Electrical Data/Timing Utopia Device-Specific Information Utopia Peripheral Register Descriptions104. Utopia Registers 105. Utopia Data Queues Receive and Transmit RegistersUtopia Electrical Data/Timing 106. Timing Requirements for UXCLK1 see FigureUxclk UrclkUxclk UXDATA70 UXADDR40Uxclav Uxenb Uxsoc Urclk URDATA70 URADDR40 N Urclav Urenb Ursoc P48 0x1FSerial RapidIO Srio Port Serial RapidIO Device-Specific InformationSerial RapidIO Peripheral Register Descriptions 112. RapidIO Control RegistersRIOBLK2EN RIOBLK2ENSTATRIOBLK3EN RIOBLK3ENSTATRIODOORBELL2ICSR RIODOORBELL2ICCRRIODOORBELL3ICSR RIODOORBELL3ICCRRioerrrstevnticrr RIOERRRSTEVNTICRR2RIOERRRSTEVNTICRR3 RIOINTDST0DECODERIOLSU4REG0 RIOLSU4REG1RIOLSU4REG2 RIOLSU4REG3RIOQUEUE4RXDMAHDP RIOQUEUE5RXDMAHDPRIOQUEUE6RXDMAHDP RIOQUEUE7RXDMAHDPRIORXUMAPL0 RIORXUMAPH0RIORXUMAPL1 RIORXUMAPH1RapidIO Peripheral-Specific Registers Riolclcfghbar RiolclcfgbarRiobaseid RiohostbaseidlockRioctrlcapt RiopwtgtidRIOSP0ERRDET RIOSP0RATEENSerial RapidIO Electrical Data/Timing 245 General-Purpose Input/Output Gpio Gpio Device-Specific InformationGpio Peripheral Register Descriptions 113. Gpio RegistersGpio Electrical Data/Timing 114. Timing Requirements for Gpio Inputs12 see FigurePulse duration, GPOx high 36P 8 Pulse duration, GPOx low 36P 8Emulation Features and Capability Advanced Event Triggering AETTrace Delay time, TCK low to TDO valid Ieee 1149.1 JtagJtag Device-Specific Information 116. Timing Requirements for Jtag Test Port see FigureRevision History C6455 Revision HistorySee ADDITIONS/MODIFICATIONS/DELETIONS Added 0.83 ns C6455-1200 1.2-GHz CPU Cycle TimeThermal Resistance Characteristics S-PBGA Package ZTZ/GTZ Thermal DataPackaging Information AIR FlowOrderable Device Status Package Pins Package Eco Plan MSL Peak TempQty Page Products Applications DSPRfid