SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

Table 7-71. Ethernet MAC (EMAC) Control Registers (continued)

HEX ADDRESS RANGE

ACRONYM

02C8 064C

TX3CP

02C8 0650

TX4CP

02C8 0654

TX5CP

02C8 0658

TX6CP

02C8 065C

TX7CP

02C8 0660

RX0CP

02C8 0664

RX1CP

02C8 0668

RX2CP

02C8 066C

RX3CP

02C8 0670

RX4CP

02C8 0674

RX5CP

02C8 0678

RX6CP

02C8 067C

RX7CP

02C8 0680 - 02C8 06FC

-

02C8 0700 - 02C8 077C

-

02C8 0780 - 02C8 0FFF

-

REGISTER NAME

Transmit Channel 3 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 4 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 5 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 6 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 7 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 0 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 1 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 2 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 3 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 4 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 5 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 6 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 7 Completion Pointer (Interrupt Acknowledge) Register

Reserved

Reserved

was State RAM Test Access Registers

Processor Read and Write Access to Head Descriptor Pointers and Interrupt Acknowledge Registers

Reserved

Table 7-72. EMAC Statistics Registers

HEX ADDRESS RANGE

ACRONYM

02C8 0200

RXGOODFRAMES

02C8 0204

RXBCASTFRAMES

02C8 0208

RXMCASTFRAMES

02C8 020C

RXPAUSEFRAMES

02C8 0210

RXCRCERRORS

02C8 0214

RXALIGNCODEERRORS

02C8 0218

RXOVERSIZED

02C8 021C

RXJABBER

02C8 0220

RXUNDERSIZED

02C8 0224

RXFRAGMENTS

02C8 0228

RXFILTERED

02C8 022C

RXQOSFILTERED

REGISTER NAME

Good Receive Frames Register

Broadcast Receive Frames Register

(Total number of good broadcast frames received)

Multicast Receive Frames Register

(Total number of good multicast frames received) Pause Receive Frames Register

Receive CRC Errors Register (Total number of frames received with CRC errors)

Receive Alignment/Code Errors Register

(Total number of frames received with alignment/code errors)

Receive Oversized Frames Register

(Total number of oversized frames received)

Receive Jabber Frames Register

(Total number of jabber frames received)

Receive Undersized Frames Register

(Total number of undersized frames received)

Receive Frame Fragments Register

Filtered Receive Frames Register

Received QOS Filtered Frames Register

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Texas Instruments SM320C6455-EP manual Emac Statistics Registers, HEX Address Range Acronym