Data Manual
Data Manual
FIXED-POINT Digital Signal Processor
C64x+ Peripheral Information and Electrical Specifications
Recommended Operating Conditions
FIXED-POINT Digital Signal Processor
Enhanced Turbo Decoder Coprocessor TCP2
Features
ZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View
ZTZ/GTZ BGA Package Bottom View
Description
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Functional Block Diagram
Functional Block Diagram
Device Characteristics
Characteristics of the C6455 Processor
Hardware Features
C6455
CPU DSP Core Description
FIXED-POINT Digital Signal Processor
C64x+ CPU DSP Core Data Paths
Memory Block Description Block Size Bytes HEX Address Range
Memory Map Summary
C6455 Memory Map Summary
02CF Ffff
02DF Ffff
03FF Ffff
0FFF Ffff
Boot Sequence
Boot Modes Supported
FIXED-POINT Digital Signal Processor
2 2nd-Level Bootloaders
Pin Assignments
Pin Map
C6455 Pin Map Bottom View Quadrant B
C6455 Pin Map Bottom View Quadrant C
C6455 Pin Map Bottom View Quadrant D
Signal Groups Description
TINPL1 TOUTL1
TINPL0
Gpio
URADDR4/PCBE0/GP2C SYSCLK4/GP1A
ACE5A ACE4A
ACE3A
ACE2A
ABE7 ABE6 ABE5 ABE4
HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 only
Hpia
CLKR1/GP0
Clks Shared
UXADDR3/MDIO
Rgmdio
UXADDR4/MDCLK
URSOC/MRXER/RMRXER
UXDATA4/MTXD4
URDATA3/MRXD3 UXDATA3/MTXD3 URDATA2/MRXD2 UXDATA2/MTXD2
UXDATA1/MTXD1/RMTXD1
UXDATA0/MTXD0/RMTXD0
Signal
IPD/IPU Description Name CLOCK/PLL Configurations
Terminal Functions
Terminal Functions
Signal Name
Type 1 IPD/IPU
Emifa 64 BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control
Emifa 64 BIT Control Signals Common to ALL Types of Memory
Emifa 64 BIT BUS Arbitration
Signal TYPE1 Name
IPD/IPU2 Description Emifa 64 BIT Address
AEA1916
AEA15
IPD/IPU Description Name
AEA6
AEA5
AEA4
Signal TYPE1 IPD/IPU2 Description Name Emifa 64 BIT Data
AED21
AED20
AED19
AED18
IPD/IPU2 Description
DDR2 Memory Controller 32 BIT Address
INTER-INTEGRATED Circuit I2C
Timer
IPD/IPU Description Name DDR2 Memory Controller 32 BIT Data
Signal TYPE1 IPD/IPU2 Description Name
Multichannel Buffered Serial Port 1 McBSP1
Multichannel Buffered Serial Port 0 McBSP0
Utopia Slave ATM Controller Transmit Interface
Utopia Slave ATM Controller Receive Interface
URADDR2/PINTA1/ GP14 URADDR1/PRST
TYPE1 IPD/IPU2 Description
Management Data INPUT/OUTPUT Mdio for Rgmii
Signal TYPE1 IPD/IPU2 Description Name Rapidio Serial Port
Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII
Device Configuration
Rgrefclk
RSV05
RSV07 RSV09
Reserved for Test
RSV13
RSV14
RSV15
RSV16
Supply Voltage Pins
Signal TYPE1 Name no
IPD/IPU2 Description Supply Voltage Monitor Pins
U16
AC6 AC9
AA1 AA6
AB7
AD5 AD7
AE6 AE8
AF1
CV DD
GND
Ground Pins
Cvdd
F20 F22 F24 G11 G13 G15 G17 G19 G21 G23
M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18
AC7 AC8
AA2 AA7
AB6
AD6
AE4 AE7
GND AF2
AH1
Development
Development Support
Device Support
Device and Development-Support Tool Nomenclature
SM=Qualifieddevice
C6000 DSP platforms
FIXED-POINT Digital Signal Processor
Device Configuration at Device Reset
C6455 Device Configuration Pins AEA190, ABA10, and Pcien
Configuration IPD PIN
IPU1
AEA14
AEA13
AEA12
AEA11
Peripheral Configuration at Device Reset
Configuration IPD Functional Description PIN
IPU
ABA0
Configuration PIN Setting Utopiaen Pcien PIN
UTOPIAEN, and MACSEL10 Peripheral Selection Utopia and Emac
Lower Upper
AUTO-INIT
Peripheral Selection After Device Reset
Peripheral States
State
Peripherals That can be This State
Static Powerdown Reset Enable Progress Disabled Enabled
Unlock the PERCFG0 register by Using the Perlock register
HEX Address Range Acronym Register Name
Device State Control Registers
Device State Control Registers
Peripheral Lock Register Description
Lockval
Bit Field Value Description 310
Lockval
Peripheral Configuration Register 0 Description
Bit Field Value Description
Bit Field
DDR2CTL
Peripheral Configuration Register 1 Description
DDR2CTL Emifactl
I2CSTAT
Peripheral Status Registers Description
Hpistat
1715
Utopiastat
SM320C6455-EP
Utopiastat Pcistat
Emac Configuration Register Emaccfg Description
Rmiirst
Emulator Buffer Powerdown Register Emubufpd Description
Emuctl
Device Status Register Description
Emifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0
Sysclkout MCBSP1EN PCI66
Pcieeai MACSEL1 MACSEL0
Utopiaen
Pcieeai
MACSEL10
BOOTMODE30
Jtag ID Jtagid Register Description
Variant Part Number Manufacturer LSB
Variant
Configuration Examples
Pullup/Pulldown Resistors
HPI VCP2 HRDY,HINT
FIXED-POINT Digital Signal Processor
Internal Buses, Bridges, and Switch Fabrics
System Interconnect
Data Switch Fabric Connections
Switched Central Resource Block Diagram
Configuration Switch Fabric
SCR Connection Matrix
C64x+ Megamodule SCR Connection
Bus Priorities
C6455 Default Bus Master Priorities
BUS Master Default Priority Control Priority Level
X+ Megamodule Block Diagram
Memory Architecture
C6455 L1P Memory Configurations
C6455 L2 Memory Configurations
Memory Protection
Bandwidth Management
Available Memory Page Protection Schemes
AID0 Bit
Power-Down Control
Megamodule Resets
Megamodule Reset Global or Local
Reset Type Megamodule
Megamodule Revision
Version Revision a
Version
Revision
C64x+ Megamodule Register Descriptions
Megamodule Interrupt Registers
Megamodule Idma Registers
Megamodule Powerdown Control Registers
Megamodule Revision Register
Megamodule Cache Configuration Registers
MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff
Megamodule L1/L2 Memory Protection Registers
L2MPPA4
L2MPPA5
L2MPPA6
L2MPPA7
L1PMPPA18
L1PMPPA19
L1PMPPA20
L1PMPPA21
HEX Address Range Acronym Register Name Comments
11. Device Configuration Registers Chip-Level Registers
10. CPU Megamodule Bandwidth Management Registers
Recommended Operating Conditions
DV DD12, DV DDRM, AV DDT, AV DDA
MIN NOM MAX Unit
AV DDA
VOS
Recommended Operating Conditions
VSS VIH VIL
Parameter Test CONDITIONS1 MIN TYP MAX Unit
VOH VOL
TDO DVDD33 = MIN IOH = MAX
DVDD33 = MIN IOL = MAX
Current DC
Parameter Information
1 3.3-V Signal Transition Levels
2 3.3-V Signal Transition Rates
Timing Parameters and Board Routing Analysis
Recommended Clock and Control Signal Transition Behavior
Power Supplies
Power-Supply Sequencing
Power-Supply Decoupling
108
Enhanced Direct Memory Access EDMA3 Controller
EDMA3 Device-Specific Information
EDMA3 Channel Synchronization Events
C6455 EDMA3 Channel Synchronization Events1
Edma Binary Event Name Event Description Channel
EDMA3 Channel Controller Registers
EDMA3 Peripheral Register Descriptions
C6455 EDMA3 Channel Synchronization Events
DCHMAP8
DCHMAP9
DCHMAP10
DCHMAP11
DCHMAP55
DCHMAP56
DCHMAP57
DCHMAP58
DRAE5
DRAEH5
DRAE6
DRAEH6
QSTAT0
QSTAT1
QSTAT2
QSTAT3
Shadow Region 0 Channel Registers
Interrupt Enable Register High
EDMA3 Parameter RAM1
EDMA3 Transfer Controller 0 Registers
EDMA3 Transfer Controller 1 Registers
EDMA3 Transfer Controller 2 Registers
121
EDMA3 Transfer Controller 3 Registers
123
Interrupts
Interrupt Sources and Interrupt Controller
10. C6455 System Event Mapping
Event Number Interrupt Event Description
XINT0
RINT1
XINT1
TINTLO0
L1PED1
Pdcint
L1PCMPA
L1PDMPA
NMI
External Interrupts Electrical Data/Timing
11. Timing Requirements for External Interrupts1 see Figure
Reset Controller
Power-on Reset POR Pin
12. Reset Types
Type Initiator
Warm Reset Reset Pin
CPU Reset
Max Reset
System Reset
Reset Priority
Reset Controller Register
Reset Type Status Register Description
Srst Mrst Wrst POR
Srst
Reset Electrical Data/Timing
14. Timing Requirements for Reset12 3see -8and Figure
720 1000/-1000 Unit
Parameter
Power-Up Timing
Resetstat
CLKIN1 CLKIN2 POR
PLL1 and PLL1 Controller
1 PLL1 Controller Device-Specific Information
Internal Clocks and Maximum Operating Frequencies
1.3 PLL1 Stabilization, Lock, and Reset Times
Clock Signal MIN MAX Unit
16. PLL1 Clock Frequency Ranges
1.2 PLL1 Controller Operating Modes
17. PLL1 Stabilization, Lock, and Reset Times
18. PLL1 Controller Registers Including Reset Controller
2 PLL1 Controller Memory Map
MIN TYP
3 PLL1 Controller Register Descriptions
3.1 PLL1 Control Register
Pllrst
Pllpwrdn
PLL Multiplier Control Register
20. PLL Multiplier Control Register Pllm Field Descriptions
Ratio
PLL Pre-Divider Control Register
Preden
PLL Controller Divider 4 Register
D4EN
PLL Controller Divider 5 Register
D5EN
PLL Controller Command Register
Goset
PLL Controller Status Register
Gostat
PLL Controller Clock Align Control Register
SYS5
Plldiv Ratio Change Status Register
SYS5 SYS4
Sysclk Status Register
SYS5ON SYS4ON SYS3ON SYS2ON
SYSCLK4
29. Timing Requirements for CLKIN1 Devices123 see Figure
PLL Modes
23. PLL2 Block Diagram
PLL2 and PLL2 Controller
1 PLL2 Controller Device-Specific Information
31. PLL2 Clock Frequency Ranges
1.2 PLL2 Controller Operating Modes
Pllref Pllen =
2 PLL2 Controller Memory Map
3 PLL2 Controller Register Descriptions
32. PLL2 Controller Registers
HEX Address Range Acronym Description
PLL Controller Divider 1 Register
D1EN
155
ALN1
SYS1
SYS1ON
4 PLL2 Controller Input Clock Electrical Data/Timing
39. Timing Requirements for CLKIN2123 see Figure
DDR2 Memory Controller
1 DDR2 Memory Controller Device-Specific Information
40. DDR2 Memory Controller Registers
2 DDR2 Memory Controller Peripheral Register Descriptions
3 DDR2 Memory Controller Electrical Data/Timing
External Memory Interface a Emifa
Emifa Device-Specific Information
Emifa Peripheral Register Descriptions
41. Emifa Registers
Aeclkin
Emifa Electrical Data/Timing
42. Timing Requirements for Aeclkin for EMIFA12 see Figure
See -33and Figure
Aeclkin AECLKOUT1
Setup = Hold =
ACEx ABE70
ABA10 AED630 Read Data
AAOE/ASOE a AAWE/ASWE a AR/W Aardy B Deasserted
Aeclkout Aardya Asserted Deasserted
Strobe Setup = Extended Strobe
ABA10 AED630
Setup time, read AEDx valid before Aeclkout high
SM320C6455-EP
BE1 BE2 BE3 BE4
EA1 EA2 EA3 EA4
ASADS/ASRE B AAOE/ASOE B AAWE/ASWEB
Write Latency =
HOLD/HOLDA Timing
HHOLDAL-HOLDL Hold time, Hold low after Holda low
DSP Owns Bus
Hold Holda
Delay time, Aeclkout high to Abusreq valid AECLKOUTx
Busreq Timing
11 I2C Peripheral
11.1 I2C Device-Specific Information
I2COAR
I2CCLKH I2CSAR
I2CXSR
I2CEMDR
11.2 I2C Peripheral Register Descriptions
51. I2C Registers
Standard Mode Fast Mode MIN MAX
11.3 I2C Electrical Data/Timing
Start Stop
SDA SCL
Stop Start
43. I2C Transmit Timings
Stop Start Repeated
Host-Port Interface HPI Peripheral
HPI Device-Specific Information
HPI Peripheral Register Descriptions
54. HPI Control Registers
HPI Electrical Data/Timing
See -56through Figure
NO.PARAMETER
HCS Has
HCNTL10
HR/W Hhwil Hstrobea
HD150
HR/W Hhwil Hstrobe a
Hrdyb
46. HPI16 Write Timing has Not Used, Tied High
47. HPI16 Write Timing has Used
48. HPI32 Read Timing has Not Used, Tied High
49. HPI32 Read Timing has Used
Has input HCNTL10 Input HR/W input
Input HCS input
51. HPI32 Write Timing has Used
Input HCS input HD310 input
Multichannel Buffered Serial Port McBSP
McBSP Device-Specific Information
58. McBSP 1 Registers
McBSP Electrical Data/Timing
720 850 1000/-1000
FIXED-POINT Digital Signal Processor
Clks
Clks Clkr
Clkx
Master Slave MIN MAX
MASTER3 Slave MIN MAX
Clkx FSX
Bit Bitn-1
Hold time, DR valid after Clkx high + 36P
Setup time, DR valid before Clkx high 18P
Master Slave MIN
198
199
Ethernet MAC Emac
Ethernet Bus
Emac Device-Specific Information
Interface Modes
Rmii
70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii Modes
Ball Number Device PIN Name
Interface Mode Clocking
Emac Peripheral Register Descriptions
71. Ethernet MAC Emac Control Registers
Macconfig
Softreset
RX6FREEBUFFER
RX7FREEBUFFER
72. Emac Statistics Registers
HEX Address Range Acronym
02C8 2000 02C8 3FFF Emac Descriptor Memory
73. Emac Control Module Registers
74. Emac Descriptor Memory
Emac Electrical Data/Timing
Mbps Gmii Only
Mrclk Input
Mtclk
Gmtclk
Output
Mrclk Input MRXD7−MRXD4GMII only
MRXD3−MRXD0
Mtclk Input MTXD7−MTXD4GMII only
MTXD3−MTXD0
Mtxen Outputs
Gmtclk Output
Emac Rmii Electrical Data/Timing
Rmrefclk Input
MRXD1-MRXD0 Mcrsdv
Mrxer Inputs 720 1000/-1000 Unit
Emac Rgmii Electrical Data/Timing
Cycle time, TXC Mbps 40*t cTXC 60*t cTXC
70. Emac Transmit Interface Timing Rgmii OperationAB
Mdio Peripheral Register Descriptions 89. Mdio Registers
Management Data Input/Output Mdio
Mdio Device-Specific Information
Delay time, Mdclk low to Mdio data output valid 100
Mdclk
Mdio input
Mdio output
Timers
Timers Device-Specific Information
Timers Peripheral Register Descriptions
92. Timer 0 Registers
TINPLx TOUTLx
Timers Electrical Data/Timing
94. Timing Requirements for Timer Inputs1 see Figure
Enhanced Viterbi-Decoder Coprocessor VCP2
16.1 VCP2 Device-Specific Information
16.2 VCP2 Peripheral Register Descriptions
96. VCP2 Registers
Enhanced Turbo Decoder Coprocessor TCP2
17.1 TCP2 Device-Specific Information
Tbhd
Tbsd
17.2 TCP2 Peripheral Register Descriptions
97. TCP2 Registers
98. Default Values for PCI Configuration Registers
Register Default Value
Peripheral Component Interconnect PCI
PCI Device-Specific Information
99. PCI Configuration Registers
PCI Peripheral Register Descriptions
100. PCI Back End Configuration Registers
101. DSP-toPCI Address Translation Registers
HEX Address Offset Acronym Register Name
102. PCI Hook Configuration Registers
103. PCI External Memory Space
48FF Ffff
49FF Ffff
4A7F Ffff
4AFF Ffff
PCI Electrical Data/Timing
Utopia Device-Specific Information
Utopia Peripheral Register Descriptions
104. Utopia Registers
105. Utopia Data Queues Receive and Transmit Registers
Utopia Electrical Data/Timing
106. Timing Requirements for UXCLK1 see Figure
Uxclk
Urclk
Uxclav Uxenb Uxsoc
Uxclk UXDATA70
UXADDR40
Urclk URDATA70 URADDR40 N Urclav Urenb Ursoc
P48 0x1F
Serial RapidIO Srio Port
Serial RapidIO Device-Specific Information
Serial RapidIO Peripheral Register Descriptions
112. RapidIO Control Registers
RIOBLK2EN
RIOBLK2ENSTAT
RIOBLK3EN
RIOBLK3ENSTAT
RIODOORBELL2ICSR
RIODOORBELL2ICCR
RIODOORBELL3ICSR
RIODOORBELL3ICCR
Rioerrrstevnticrr
RIOERRRSTEVNTICRR2
RIOERRRSTEVNTICRR3
RIOINTDST0DECODE
RIOLSU4REG0
RIOLSU4REG1
RIOLSU4REG2
RIOLSU4REG3
RIOQUEUE4RXDMAHDP
RIOQUEUE5RXDMAHDP
RIOQUEUE6RXDMAHDP
RIOQUEUE7RXDMAHDP
RIORXUMAPL0
RIORXUMAPH0
RIORXUMAPL1
RIORXUMAPH1
RapidIO Peripheral-Specific Registers
Riolclcfghbar
Riolclcfgbar
Riobaseid
Riohostbaseidlock
Rioctrlcapt
Riopwtgtid
RIOSP0ERRDET
RIOSP0RATEEN
Serial RapidIO Electrical Data/Timing
245
General-Purpose Input/Output Gpio
Gpio Device-Specific Information
Gpio Peripheral Register Descriptions
113. Gpio Registers
Gpio Electrical Data/Timing
114. Timing Requirements for Gpio Inputs12 see Figure
Pulse duration, GPOx high 36P 8
Pulse duration, GPOx low 36P 8
Trace
Emulation Features and Capability
Advanced Event Triggering AET
Delay time, TCK low to TDO valid
Ieee 1149.1 Jtag
Jtag Device-Specific Information
116. Timing Requirements for Jtag Test Port see Figure
Revision History
C6455 Revision History
See ADDITIONS/MODIFICATIONS/DELETIONS
Added 0.83 ns C6455-1200 1.2-GHz CPU Cycle Time
Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZ
Thermal Data
Packaging Information
AIR Flow
Qty
Orderable Device Status Package Pins Package Eco Plan
MSL Peak Temp
Page
Rfid
Products Applications
DSP
