Texas Instruments SM320C6455-EP guide

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

Table 7-86. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps(1) (see Figure 7-69)

			-720
			-850
NO.			A-1000/-1000		UNIT
			-1200
			MIN	MAX
5	tsu(RXD-RXCH)	Setup time, receive selected signals valid before RXC (at DSP) high/low	1.0		ns
6	th(RXCH-RXD)	Hold time, receive selected signals valid after RXC (at DSP) high/low	1.0		ns

(1)For RGMII, receive selected signals include: RXD[3:0] and RXCTL.

RXC (at DSP)(B)

RXD[3:0](A)

1

4 2

3

4

5

1st Half-byte

2nd Half-byte		6

RXD[3:0]RXD[7:4]

RXCTL(A)

RXDVRXERR

A.Data and control information is received using both edges of the clocks. RXD[3:0] carries data bits 3-0 on the rising edge of RXC and data bits 7-4 on the falling edge of RXC. Similarly, RXCTL carries RXDV on rising edge of RXC and RXERR on falling edge

B.RXC must be externally delayed relative to the data and control pins.

Figure 7-69. EMAC Receive Interface Timing [RGMII Operation](A)(B)

Table 7-87. Switching Characteristics Over Recommended Operating Conditions for TXC - RGMII

Operation for 10/100/1000 Mbit/s (see Figure 7-70)

				-720
				-850
NO.				A-1000/-1000		UNIT
				-1200
				MIN	MAX
			10 Mbps	360	440
1	tc(TXC)	Cycle time, TXC	100 Mbps	36	44	ns
			1000 Mbps	7.2	8.8
			10 Mbps	0.40*tc(TXC)	0.60*tc(TXC)
2	tw(TXCH)	Pulse duration, TXC high	100 Mbps	0.40*tc(TXC)	0.60*tc(TXC)	ns
			1000 Mbps	0.45*tc(TXC)	0.55*tc(TXC)
			10 Mbps	0.40*tc(TXC)	0.60*tc(TXC)
3	tw(TXCL)	Pulse duration, TXC low	100 Mbps	0.40*tc(TXC)	0.60*tc(TXC)	ns
			1000 Mbps	0.45*tc(TXC)	0.55*tc(TXC)
			10 Mbps		0.75
4	tt(TXC)	Transition time, TXC	100 Mbps		0.75	ns
			1000 Mbps		0.75

214

C64x+ Peripheral Information and Electrical Specifications

Submit Documentation Feedback

Image 214

Texas Instruments SM320C6455-EP manual Cycle time, TXC Mbps 40*t cTXC 60*t cTXC

Contents

Data Manual Data Manual FIXED-POINT Digital Signal Processor C64x+ Peripheral Information and Electrical Specifications Recommended Operating Conditions FIXED-POINT Digital Signal Processor Enhanced Turbo Decoder Coprocessor TCP2 Features Description ZTZ/GTZ BGA Package Bottom ViewZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View Submit Documentation Feedback Functional Block Diagram Functional Block Diagram Hardware Features Device CharacteristicsCharacteristics of the C6455 Processor C6455 CPU DSP Core Description FIXED-POINT Digital Signal Processor C64x+ CPU DSP Core Data Paths C6455 Memory Map Summary Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range 03FF Ffff 02CF Ffff02DF Ffff 0FFF Ffff Boot Sequence Boot Modes Supported FIXED-POINT Digital Signal Processor 2 2nd-Level Bootloaders Pin Assignments Pin Map C6455 Pin Map Bottom View Quadrant B C6455 Pin Map Bottom View Quadrant C C6455 Pin Map Bottom View Quadrant D Signal Groups Description Gpio TINPL1 TOUTL1TINPL0 URADDR4/PCBE0/GP2C SYSCLK4/GP1A ACE2A ACE5A ACE4AACE3A ABE7 ABE6 ABE5 ABE4 CLKR1/GP0 HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 onlyHpia Clks Shared UXADDR4/MDCLK UXADDR3/MDIORgmdio URSOC/MRXER/RMRXER UXDATA1/MTXD1/RMTXD1 UXDATA4/MTXD4URDATA3/MRXD3 UXDATA3/MTXD3 URDATA2/MRXD2 UXDATA2/MTXD2 UXDATA0/MTXD0/RMTXD0 Terminal Functions SignalIPD/IPU Description Name CLOCK/PLL Configurations Terminal Functions Signal Name Type 1 IPD/IPU Emifa 64 BIT BUS Arbitration Emifa 64 BIT Control Signals Common to ALL Types of MemoryEmifa 64 BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control AEA1916 Signal TYPE1 NameIPD/IPU2 Description Emifa 64 BIT Address AEA15 AEA5 IPD/IPU Description NameAEA6 AEA4 Signal TYPE1 IPD/IPU2 Description Name Emifa 64 BIT Data AED19 AED21AED20 AED18 IPD/IPU2 Description DDR2 Memory Controller 32 BIT Address IPD/IPU Description Name DDR2 Memory Controller 32 BIT Data TimerINTER-INTEGRATED Circuit I2C Multichannel Buffered Serial Port 0 McBSP0 Signal TYPE1 IPD/IPU2 Description NameMultichannel Buffered Serial Port 1 McBSP1 Utopia Slave ATM Controller Transmit Interface TYPE1 IPD/IPU2 Description URADDR2/PINTA1/ GP14 URADDR1/PRSTUtopia Slave ATM Controller Receive Interface Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII Signal TYPE1 IPD/IPU2 Description Name Rapidio Serial PortManagement Data INPUT/OUTPUT Mdio for Rgmii Device Configuration RSV07 RSV09 RgrefclkRSV05 Reserved for Test RSV15 RSV13RSV14 RSV16 IPD/IPU2 Description Supply Voltage Monitor Pins Signal TYPE1 Name noSupply Voltage Pins U16 AB7 AA1 AA6AC6 AC9 AF1 AD5 AD7AE6 AE8 CV DD Cvdd Ground PinsGND F20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AB6 AA2 AA7AC7 AC8 GND AF2 AD6AE4 AE7 AH1 Device Support DevelopmentDevelopment Support Device and Development-Support Tool Nomenclature SM=Qualifieddevice C6000 DSP platforms FIXED-POINT Digital Signal Processor Configuration IPD PIN Device Configuration at Device ResetC6455 Device Configuration Pins AEA190, ABA10, and Pcien IPU1 AEA12 AEA14AEA13 AEA11 IPU Peripheral Configuration at Device ResetConfiguration IPD Functional Description PIN ABA0 Lower Upper Configuration PIN Setting Utopiaen Pcien PINUTOPIAEN, and MACSEL10 Peripheral Selection Utopia and Emac AUTO-INIT State Peripheral Selection After Device ResetPeripheral States Peripherals That can be This State Static Powerdown Reset Enable Progress Disabled Enabled Unlock the PERCFG0 register by Using the Perlock register Device State Control Registers Device State Control RegistersHEX Address Range Acronym Register Name Bit Field Value Description 310 Peripheral Lock Register DescriptionLockval Lockval Peripheral Configuration Register 0 Description Bit Field Value Description Bit Field DDR2CTL Emifactl Peripheral Configuration Register 1 DescriptionDDR2CTL Hpistat Peripheral Status Registers DescriptionI2CSTAT 1715 Utopiastat Pcistat SM320C6455-EPUtopiastat Emac Configuration Register Emaccfg Description Rmiirst Emulator Buffer Powerdown Register Emubufpd Description Emuctl Sysclkout MCBSP1EN PCI66 Device Status Register DescriptionEmifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0 Pcieeai MACSEL1 MACSEL0 MACSEL10 PcieeaiUtopiaen Variant Part Number Manufacturer LSB BOOTMODE30Jtag ID Jtagid Register Description Variant Configuration Examples Pullup/Pulldown Resistors HPI VCP2 HRDY,HINT FIXED-POINT Digital Signal Processor Internal Buses, Bridges, and Switch Fabrics System Interconnect Data Switch Fabric Connections Switched Central Resource Block Diagram Configuration Switch Fabric SCR Connection Matrix C64x+ Megamodule SCR Connection BUS Master Default Priority Control Priority Level C6455 Default Bus Master PrioritiesBus Priorities X+ Megamodule Block Diagram Memory Architecture C6455 L1P Memory Configurations C6455 L2 Memory Configurations Available Memory Page Protection Schemes Memory ProtectionBandwidth Management AID0 Bit Megamodule Reset Global or Local Power-Down ControlMegamodule Resets Reset Type Megamodule Version Megamodule RevisionVersion Revision a Revision C64x+ Megamodule Register Descriptions Megamodule Interrupt Registers Megamodule Revision Register Megamodule Powerdown Control RegistersMegamodule Idma Registers Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA6 L2MPPA4L2MPPA5 L2MPPA7 L1PMPPA20 L1PMPPA18L1PMPPA19 L1PMPPA21 10. CPU Megamodule Bandwidth Management Registers 11. Device Configuration Registers Chip-Level RegistersHEX Address Range Acronym Register Name Comments MIN NOM MAX Unit Recommended Operating ConditionsDV DD12, DV DDRM, AV DDT, AV DDA AV DDA VSS VIH VIL Recommended Operating ConditionsVOS TDO DVDD33 = MIN IOH = MAX Parameter Test CONDITIONS1 MIN TYP MAX UnitVOH VOL DVDD33 = MIN IOL = MAX Current DC 2 3.3-V Signal Transition Rates 1 3.3-V Signal Transition LevelsParameter Information Timing Parameters and Board Routing Analysis Power-Supply Sequencing Recommended Clock and Control Signal Transition BehaviorPower Supplies Power-Supply Decoupling 108 Enhanced Direct Memory Access EDMA3 Controller C6455 EDMA3 Channel Synchronization Events1 EDMA3 Device-Specific InformationEDMA3 Channel Synchronization Events Edma Binary Event Name Event Description Channel C6455 EDMA3 Channel Synchronization Events EDMA3 Peripheral Register DescriptionsEDMA3 Channel Controller Registers DCHMAP10 DCHMAP8DCHMAP9 DCHMAP11 DCHMAP57 DCHMAP55DCHMAP56 DCHMAP58 DRAE6 DRAE5DRAEH5 DRAEH6 QSTAT2 QSTAT0QSTAT1 QSTAT3 Shadow Region 0 Channel Registers Interrupt Enable Register High EDMA3 Parameter RAM1 EDMA3 Transfer Controller 0 Registers EDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 121 EDMA3 Transfer Controller 3 Registers 123 10. C6455 System Event Mapping InterruptsInterrupt Sources and Interrupt Controller Event Number Interrupt Event Description XINT1 XINT0RINT1 TINTLO0 L1PCMPA L1PED1Pdcint L1PDMPA 11. Timing Requirements for External Interrupts1 see Figure External Interrupts Electrical Data/TimingNMI 12. Reset Types Reset ControllerPower-on Reset POR Pin Type Initiator Warm Reset Reset Pin System Reset Max ResetCPU Reset Reset Priority Srst Mrst Wrst POR Reset Controller RegisterReset Type Status Register Description Srst 720 1000/-1000 Unit Reset Electrical Data/Timing14. Timing Requirements for Reset12 3see -8and Figure Parameter Power-Up Timing Resetstat CLKIN1 CLKIN2 POR PLL1 and PLL1 Controller 1 PLL1 Controller Device-Specific Information Internal Clocks and Maximum Operating Frequencies 16. PLL1 Clock Frequency Ranges 1.3 PLL1 Stabilization, Lock, and Reset TimesClock Signal MIN MAX Unit 1.2 PLL1 Controller Operating Modes 2 PLL1 Controller Memory Map 17. PLL1 Stabilization, Lock, and Reset Times18. PLL1 Controller Registers Including Reset Controller MIN TYP Pllrst 3 PLL1 Controller Register Descriptions3.1 PLL1 Control Register Pllpwrdn PLL Multiplier Control Register 20. PLL Multiplier Control Register Pllm Field Descriptions Preden PLL Pre-Divider Control RegisterRatio PLL Controller Divider 4 Register D4EN PLL Controller Divider 5 Register D5EN PLL Controller Command Register Goset PLL Controller Status Register Gostat PLL Controller Clock Align Control Register SYS5 SYS4 Plldiv Ratio Change Status RegisterSYS5 Sysclk Status Register SYS5ON SYS4ON SYS3ON SYS2ON PLL Modes 29. Timing Requirements for CLKIN1 Devices123 see FigureSYSCLK4 23. PLL2 Block Diagram PLL2 and PLL2 Controller 1.2 PLL2 Controller Operating Modes 1 PLL2 Controller Device-Specific Information31. PLL2 Clock Frequency Ranges Pllref Pllen = 32. PLL2 Controller Registers 2 PLL2 Controller Memory Map3 PLL2 Controller Register Descriptions HEX Address Range Acronym Description PLL Controller Divider 1 Register D1EN 155 ALN1 SYS1 SYS1ON 4 PLL2 Controller Input Clock Electrical Data/Timing 39. Timing Requirements for CLKIN2123 see Figure DDR2 Memory Controller 1 DDR2 Memory Controller Device-Specific Information 3 DDR2 Memory Controller Electrical Data/Timing 2 DDR2 Memory Controller Peripheral Register Descriptions40. DDR2 Memory Controller Registers External Memory Interface a Emifa Emifa Device-Specific Information Emifa Peripheral Register Descriptions 41. Emifa Registers 42. Timing Requirements for Aeclkin for EMIFA12 see Figure Emifa Electrical Data/TimingAeclkin See -33and Figure Aeclkin AECLKOUT1 ABA10 AED630 Read Data Setup = Hold =ACEx ABE70 AAOE/ASOE a AAWE/ASWE a AR/W Aardy B Deasserted ABA10 AED630 Strobe Setup = Extended StrobeAeclkout Aardya Asserted Deasserted Setup time, read AEDx valid before Aeclkout high EA1 EA2 EA3 EA4 SM320C6455-EPBE1 BE2 BE3 BE4 ASADS/ASRE B AAOE/ASOE B AAWE/ASWEB Write Latency = DSP Owns Bus HOLD/HOLDA TimingHHOLDAL-HOLDL Hold time, Hold low after Holda low Hold Holda Delay time, Aeclkout high to Abusreq valid AECLKOUTx Busreq Timing 11 I2C Peripheral 11.1 I2C Device-Specific Information I2CXSR I2COARI2CCLKH I2CSAR I2CEMDR 11.2 I2C Peripheral Register Descriptions 51. I2C Registers Standard Mode Fast Mode MIN MAX 11.3 I2C Electrical Data/Timing Stop Start SDA SCLStart Stop 43. I2C Transmit Timings Stop Start Repeated HPI Peripheral Register Descriptions Host-Port Interface HPI PeripheralHPI Device-Specific Information 54. HPI Control Registers HPI Electrical Data/Timing See -56through Figure NO.PARAMETER HR/W Hhwil Hstrobea HCS HasHCNTL10 HD150 HR/W Hhwil Hstrobe a Hrdyb 46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used 48. HPI32 Read Timing has Not Used, Tied High 49. HPI32 Read Timing has Used Has input HCNTL10 Input HR/W input Input HCS input 51. HPI32 Write Timing has Used Input HCS input HD310 input Multichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers McBSP Electrical Data/Timing 720 850 1000/-1000 FIXED-POINT Digital Signal Processor Clkx Clks ClkrClks Clkx FSX Master Slave MIN MAXMASTER3 Slave MIN MAX Bit Bitn-1 Master Slave MIN Setup time, DR valid before Clkx high 18PHold time, DR valid after Clkx high + 36P 198 199 Ethernet MAC Emac Ethernet Bus Emac Device-Specific Information Interface Modes Ball Number Device PIN Name 70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii ModesRmii Interface Mode Clocking Emac Peripheral Register Descriptions 71. Ethernet MAC Emac Control Registers RX6FREEBUFFER MacconfigSoftreset RX7FREEBUFFER 72. Emac Statistics Registers HEX Address Range Acronym 74. Emac Descriptor Memory 73. Emac Control Module Registers02C8 2000 02C8 3FFF Emac Descriptor Memory Mrclk Input Emac Electrical Data/TimingMbps Gmii Only Mtclk Mrclk Input MRXD7−MRXD4GMII only GmtclkOutput MRXD3−MRXD0 Mtxen Outputs Mtclk Input MTXD7−MTXD4GMII onlyMTXD3−MTXD0 Gmtclk Output Emac Rmii Electrical Data/Timing Rmrefclk Input MRXD1-MRXD0 Mcrsdv Mrxer Inputs 720 1000/-1000 Unit Emac Rgmii Electrical Data/Timing Cycle time, TXC Mbps 40*t cTXC 60*t cTXC 70. Emac Transmit Interface Timing Rgmii OperationAB Mdio Device-Specific Information Management Data Input/Output MdioMdio Peripheral Register Descriptions 89. Mdio Registers Mdio input Delay time, Mdclk low to Mdio data output valid 100Mdclk Mdio output Timers Peripheral Register Descriptions TimersTimers Device-Specific Information 92. Timer 0 Registers 94. Timing Requirements for Timer Inputs1 see Figure Timers Electrical Data/TimingTINPLx TOUTLx 16.2 VCP2 Peripheral Register Descriptions Enhanced Viterbi-Decoder Coprocessor VCP216.1 VCP2 Device-Specific Information 96. VCP2 Registers Tbhd Enhanced Turbo Decoder Coprocessor TCP217.1 TCP2 Device-Specific Information Tbsd 17.2 TCP2 Peripheral Register Descriptions 97. TCP2 Registers Peripheral Component Interconnect PCI 98. Default Values for PCI Configuration RegistersRegister Default Value PCI Device-Specific Information 99. PCI Configuration Registers PCI Peripheral Register Descriptions 100. PCI Back End Configuration Registers 101. DSP-toPCI Address Translation Registers 103. PCI External Memory Space 102. PCI Hook Configuration RegistersHEX Address Offset Acronym Register Name 4A7F Ffff 48FF Ffff49FF Ffff 4AFF Ffff PCI Electrical Data/Timing 104. Utopia Registers Utopia Device-Specific InformationUtopia Peripheral Register Descriptions 105. Utopia Data Queues Receive and Transmit Registers Uxclk Utopia Electrical Data/Timing106. Timing Requirements for UXCLK1 see Figure Urclk UXADDR40 Uxclk UXDATA70Uxclav Uxenb Uxsoc Urclk URDATA70 URADDR40 N Urclav Urenb Ursoc P48 0x1F Serial RapidIO Peripheral Register Descriptions Serial RapidIO Srio PortSerial RapidIO Device-Specific Information 112. RapidIO Control Registers RIOBLK3EN RIOBLK2ENRIOBLK2ENSTAT RIOBLK3ENSTAT RIODOORBELL3ICSR RIODOORBELL2ICSRRIODOORBELL2ICCR RIODOORBELL3ICCR RIOERRRSTEVNTICRR3 RioerrrstevnticrrRIOERRRSTEVNTICRR2 RIOINTDST0DECODE RIOLSU4REG2 RIOLSU4REG0RIOLSU4REG1 RIOLSU4REG3 RIOQUEUE6RXDMAHDP RIOQUEUE4RXDMAHDPRIOQUEUE5RXDMAHDP RIOQUEUE7RXDMAHDP RIORXUMAPL1 RIORXUMAPL0RIORXUMAPH0 RIORXUMAPH1 RapidIO Peripheral-Specific Registers Riobaseid RiolclcfghbarRiolclcfgbar Riohostbaseidlock RIOSP0ERRDET RioctrlcaptRiopwtgtid RIOSP0RATEEN Serial RapidIO Electrical Data/Timing 245 Gpio Peripheral Register Descriptions General-Purpose Input/Output GpioGpio Device-Specific Information 113. Gpio Registers Pulse duration, GPOx high 36P 8 Gpio Electrical Data/Timing114. Timing Requirements for Gpio Inputs12 see Figure Pulse duration, GPOx low 36P 8 Advanced Event Triggering AET Emulation Features and CapabilityTrace Jtag Device-Specific Information Delay time, TCK low to TDO validIeee 1149.1 Jtag 116. Timing Requirements for Jtag Test Port see Figure See ADDITIONS/MODIFICATIONS/DELETIONS Revision HistoryC6455 Revision History Added 0.83 ns C6455-1200 1.2-GHz CPU Cycle Time Packaging Information Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZThermal Data AIR Flow MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanQty Page DSP Products ApplicationsRfid