Texas Instruments SM320C6455-EP 11.3 I2C Electrical Data/Timing, Standard Mode Fast Mode MIN MAX

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.11.3I2C Electrical Data/Timing

7.11.3.1Inter-Integrated Circuits (I2C) Timing

Table 7-52. Timing Requirements for I2C Timings(1) (see Figure 7-42)

NO.

1 tc(SCL)

2tsu(SCLH-SDAL)

3th(SCLL-SDAL)

4 tw(SCLL)

5 tw(SCLH)

6tsu(SDAV-SDLH)

7th(SDA-SDLL)

8tw(SDAH)

9 tr(SDA)

10tr(SCL)

11 tf(SDA)

12 tf(SCL)

13tsu(SCLH-SDAH)

14 tw(SP)

15 Cb (5)

Cycle time, SCL

Setup time, SCL high before SDA low (for a repeated START condition)

Hold time, SCL low after SDA low (for a START and a repeated START condition)

Pulse duration, SCL low

Pulse duration, SCL high

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low (For I2C bus™ devices)

Pulse duration, SDA high between STOP and

START conditions

Rise time, SDA

Rise time, SCL

Fall time, SDA

Fall time, SCL

Setup time, SCL high before SDA high (for STOP condition)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

		-720
		-850
	A-1000/-1000				UNIT
	-1200
STANDARD MODE		FAST MODE
MIN	MAX	MIN		MAX
10		2.5			μs
4.7		0.6			μs
4		0.6			μs
4.7		1.3			μs
4		0.6			μs
250		100(2)			ns
0(3)		0(3)		0.9(4)	μs
4.7		1.3			μs
	1000	20 + 0.1Cb	(5)	300	ns
	1000	20 + 0.1Cb	(5)	300	ns
	300	20 + 0.1Cb	(5)	300	ns
	300	20 + 0.1Cb	(5)	300	ns
4		0.6			μs
			0	50	ns
	400			400	pF

(1)The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.

(2)A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus™ system, but the requirement tsu(SDA-SCLH)≥250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch

the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released.

(3)A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.

(4)The maximum th(SDA-SCLL)has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.

(5)Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

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