Texas Instruments SM320C6455-EP manual Setup = Hold =, ACEx ABE70, ABA10 AED630 Read Data

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

Table 7-45. Switching Characteristics Over Recommended Operating Conditions for Asynchronous

Memory Cycles for EMIFA Module(1)(2)(3) (see Figure 7-33and Figure 7-34)

NO.

1tosu(SELV-AOEL)

2toh(AOEH-SELIV)

10td(EKOH-AOEV)

11tosu(SELV-AWEL)

12toh(AWEH-SELIV)

13td(EKOH-AWEV)

	-720
	-850
PARAMETER	A-1000/-1000		UNIT
	-1200
	MIN	MAX
Output setup time, select signals valid to AAOE low	RS * E – 1.5		ns
Output hold time, AAOE high to select signals invalid	RS * E – 1.9		ns
Delay time, AECLKOUT high to AAOE valid	1	7	ns
Output setup time, select signals valid to AAWE low	WS * E – 1.7		ns
Output hold time, AAWE high to select signals invalid	WH * E – 1.8		ns
Delay time, AECLKOUT high to AAWE valid	1.3	7.1	ns

(1)E = AECLKOUT period in ns for EMIFA

(2)RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are programmed via the EMIFA CE Configuration registers (CEnCFG).

(3)Select signals for EMIFA include: ACEx, ABE[7:0], AEA[19:0], ABA[1:0]; and for EMIFA writes, also include AR/W, AED[63:0].

		Strobe = 4
	Setup = 1		Hold = 1
AECLKOUT	1		2
ACEx	1		2
ABE[7:0]		Byte Enables	2
AEA[19:0]/	1
		Address
ABA[1:0]
		3	4
AED[63:0]		Read Data
AAOE/ASOE(A)	10	10
AAWE/ASWE(A)
AR/W
AARDY(B)		DEASSERTED

AAAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous memory accesses.

BPolarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register (AWCC).

Figure 7-33. Asynchronous Memory Read Timing for EMIFA

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