SYS5 SYS4 | Texas Instruments SM320C6455-EP specs

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.7.3.9 PLLDIV Ratio Change Status Register

Whenever a different ratio is written to the PLLDIVn registers, the PLLCTRL flags the change in the PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controller will only change the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that changed clocks will be automatically aligned to other clocks. The PLLDIV divider ratio change status register is shown in Figure 7-19and described in Table 7-27.

31							16
			Reserved
			R-0
15			5	4	3	2	0
			Reserved	SYS5	SYS4	Reserved
			R-0	R-0	R-0	R-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
	Figure 7-19. PLLDIV Divider Ratio Change Status Register (DCHANGE) [Hex Address: 029A 0144]
	Table 7-27. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions
Bit	Field	Value	Description
31:5	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
4	SYS5		Identifies when the SYSCLK5 divide ratio has been modified.
		0	SYSCLK5 ratio has not been modified. When GOSET is set, SYSCLK5 will not be affected.
		1	SYSCLK5 ratio has been modified. When GOSET is set, SYSCLK5 will change to the new ratio.
3	SYS4		Identifies when the SYSCLK4 divide ratio has been modified.
		0	SYSCLK4 ratio has not been modified. When GOSET is set, SYSCLK4 will not be affected.
		1	SYSCLK4 ratio has been modified. When GOSET is set, SYSCLK4 will change to the new ratio.
2:0	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

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C64x+ Peripheral Information and Electrical Specifications

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Texas Instruments SM320C6455-EP manual Plldiv Ratio Change Status Register, SYS5 SYS4

Contents

Data Manual Data Manual FIXED-POINT Digital Signal Processor C64x+ Peripheral Information and Electrical Specifications Recommended Operating Conditions FIXED-POINT Digital Signal Processor Enhanced Turbo Decoder Coprocessor TCP2 Features Description ZTZ/GTZ BGA Package Bottom ViewZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View Submit Documentation Feedback Functional Block Diagram Functional Block Diagram Device Characteristics Characteristics of the C6455 ProcessorHardware Features C6455 CPU DSP Core Description FIXED-POINT Digital Signal Processor C64x+ CPU DSP Core Data Paths C6455 Memory Map Summary Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range 02CF Ffff 02DF Ffff03FF Ffff 0FFF Ffff Boot Sequence Boot Modes Supported FIXED-POINT Digital Signal Processor 2 2nd-Level Bootloaders Pin Assignments Pin Map C6455 Pin Map Bottom View Quadrant B C6455 Pin Map Bottom View Quadrant C C6455 Pin Map Bottom View Quadrant D Signal Groups Description TINPL1 TOUTL1 TINPL0Gpio URADDR4/PCBE0/GP2C SYSCLK4/GP1A ACE5A ACE4A ACE3AACE2A ABE7 ABE6 ABE5 ABE4 HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 only HpiaCLKR1/GP0 Clks Shared UXADDR3/MDIO RgmdioUXADDR4/MDCLK URSOC/MRXER/RMRXER UXDATA4/MTXD4 URDATA3/MRXD3 UXDATA3/MTXD3 URDATA2/MRXD2 UXDATA2/MTXD2UXDATA1/MTXD1/RMTXD1 UXDATA0/MTXD0/RMTXD0 Signal IPD/IPU Description Name CLOCK/PLL ConfigurationsTerminal Functions Terminal Functions Signal Name Type 1 IPD/IPU Emifa 64 BIT BUS Arbitration Emifa 64 BIT Control Signals Common to ALL Types of MemoryEmifa 64 BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control Signal TYPE1 Name IPD/IPU2 Description Emifa 64 BIT AddressAEA1916 AEA15 IPD/IPU Description Name AEA6AEA5 AEA4 Signal TYPE1 IPD/IPU2 Description Name Emifa 64 BIT Data AED21 AED20AED19 AED18 IPD/IPU2 Description DDR2 Memory Controller 32 BIT Address IPD/IPU Description Name DDR2 Memory Controller 32 BIT Data TimerINTER-INTEGRATED Circuit I2C Signal TYPE1 IPD/IPU2 Description Name Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 Utopia Slave ATM Controller Transmit Interface TYPE1 IPD/IPU2 Description URADDR2/PINTA1/ GP14 URADDR1/PRSTUtopia Slave ATM Controller Receive Interface Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII Signal TYPE1 IPD/IPU2 Description Name Rapidio Serial PortManagement Data INPUT/OUTPUT Mdio for Rgmii Device Configuration Rgrefclk RSV05RSV07 RSV09 Reserved for Test RSV13 RSV14RSV15 RSV16 IPD/IPU2 Description Supply Voltage Monitor Pins Signal TYPE1 Name noSupply Voltage Pins U16 AB7 AA1 AA6AC6 AC9 AD5 AD7 AE6 AE8AF1 CV DD Cvdd Ground PinsGND F20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AB6 AA2 AA7AC7 AC8 AD6 AE4 AE7GND AF2 AH1 Development Development SupportDevice Support Device and Development-Support Tool Nomenclature SM=Qualifieddevice C6000 DSP platforms FIXED-POINT Digital Signal Processor Device Configuration at Device Reset C6455 Device Configuration Pins AEA190, ABA10, and PcienConfiguration IPD PIN IPU1 AEA14 AEA13AEA12 AEA11 Peripheral Configuration at Device Reset Configuration IPD Functional Description PINIPU ABA0 Configuration PIN Setting Utopiaen Pcien PIN UTOPIAEN, and MACSEL10 Peripheral Selection Utopia and EmacLower Upper AUTO-INIT Peripheral Selection After Device Reset Peripheral StatesState Peripherals That can be This State Static Powerdown Reset Enable Progress Disabled Enabled Unlock the PERCFG0 register by Using the Perlock register Device State Control Registers Device State Control RegistersHEX Address Range Acronym Register Name Peripheral Lock Register Description LockvalBit Field Value Description 310 Lockval Peripheral Configuration Register 0 Description Bit Field Value Description Bit Field DDR2CTL Emifactl Peripheral Configuration Register 1 DescriptionDDR2CTL Hpistat Peripheral Status Registers DescriptionI2CSTAT 1715 Utopiastat Pcistat SM320C6455-EPUtopiastat Emac Configuration Register Emaccfg Description Rmiirst Emulator Buffer Powerdown Register Emubufpd Description Emuctl Device Status Register Description Emifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0Sysclkout MCBSP1EN PCI66 Pcieeai MACSEL1 MACSEL0 MACSEL10 PcieeaiUtopiaen BOOTMODE30 Jtag ID Jtagid Register DescriptionVariant Part Number Manufacturer LSB Variant Configuration Examples Pullup/Pulldown Resistors HPI VCP2 HRDY,HINT FIXED-POINT Digital Signal Processor Internal Buses, Bridges, and Switch Fabrics System Interconnect Data Switch Fabric Connections Switched Central Resource Block Diagram Configuration Switch Fabric SCR Connection Matrix C64x+ Megamodule SCR Connection BUS Master Default Priority Control Priority Level C6455 Default Bus Master PrioritiesBus Priorities X+ Megamodule Block Diagram Memory Architecture C6455 L1P Memory Configurations C6455 L2 Memory Configurations Memory Protection Bandwidth ManagementAvailable Memory Page Protection Schemes AID0 Bit Power-Down Control Megamodule ResetsMegamodule Reset Global or Local Reset Type Megamodule Megamodule Revision Version Revision aVersion Revision C64x+ Megamodule Register Descriptions Megamodule Interrupt Registers Megamodule Revision Register Megamodule Powerdown Control RegistersMegamodule Idma Registers Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA4 L2MPPA5L2MPPA6 L2MPPA7 L1PMPPA18 L1PMPPA19L1PMPPA20 L1PMPPA21 10. CPU Megamodule Bandwidth Management Registers 11. Device Configuration Registers Chip-Level RegistersHEX Address Range Acronym Register Name Comments Recommended Operating Conditions DV DD12, DV DDRM, AV DDT, AV DDAMIN NOM MAX Unit AV DDA VSS VIH VIL Recommended Operating ConditionsVOS Parameter Test CONDITIONS1 MIN TYP MAX Unit VOH VOLTDO DVDD33 = MIN IOH = MAX DVDD33 = MIN IOL = MAX Current DC 2 3.3-V Signal Transition Rates 1 3.3-V Signal Transition LevelsParameter Information Timing Parameters and Board Routing Analysis Recommended Clock and Control Signal Transition Behavior Power SuppliesPower-Supply Sequencing Power-Supply Decoupling 108 Enhanced Direct Memory Access EDMA3 Controller EDMA3 Device-Specific Information EDMA3 Channel Synchronization EventsC6455 EDMA3 Channel Synchronization Events1 Edma Binary Event Name Event Description Channel C6455 EDMA3 Channel Synchronization Events EDMA3 Peripheral Register DescriptionsEDMA3 Channel Controller Registers DCHMAP8 DCHMAP9DCHMAP10 DCHMAP11 DCHMAP55 DCHMAP56DCHMAP57 DCHMAP58 DRAE5 DRAEH5DRAE6 DRAEH6 QSTAT0 QSTAT1QSTAT2 QSTAT3 Shadow Region 0 Channel Registers Interrupt Enable Register High EDMA3 Parameter RAM1 EDMA3 Transfer Controller 0 Registers EDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 121 EDMA3 Transfer Controller 3 Registers 123 Interrupts Interrupt Sources and Interrupt Controller10. C6455 System Event Mapping Event Number Interrupt Event Description XINT0 RINT1XINT1 TINTLO0 L1PED1 PdcintL1PCMPA L1PDMPA 11. Timing Requirements for External Interrupts1 see Figure External Interrupts Electrical Data/TimingNMI Reset Controller Power-on Reset POR Pin12. Reset Types Type Initiator Warm Reset Reset Pin System Reset Max ResetCPU Reset Reset Priority Reset Controller Register Reset Type Status Register DescriptionSrst Mrst Wrst POR Srst Reset Electrical Data/Timing 14. Timing Requirements for Reset12 3see -8and Figure720 1000/-1000 Unit Parameter Power-Up Timing Resetstat CLKIN1 CLKIN2 POR PLL1 and PLL1 Controller 1 PLL1 Controller Device-Specific Information Internal Clocks and Maximum Operating Frequencies 1.3 PLL1 Stabilization, Lock, and Reset Times Clock Signal MIN MAX Unit16. PLL1 Clock Frequency Ranges 1.2 PLL1 Controller Operating Modes 17. PLL1 Stabilization, Lock, and Reset Times 18. PLL1 Controller Registers Including Reset Controller2 PLL1 Controller Memory Map MIN TYP 3 PLL1 Controller Register Descriptions 3.1 PLL1 Control RegisterPllrst Pllpwrdn PLL Multiplier Control Register 20. PLL Multiplier Control Register Pllm Field Descriptions Preden PLL Pre-Divider Control RegisterRatio PLL Controller Divider 4 Register D4EN PLL Controller Divider 5 Register D5EN PLL Controller Command Register Goset PLL Controller Status Register Gostat PLL Controller Clock Align Control Register SYS5 SYS4 Plldiv Ratio Change Status RegisterSYS5 Sysclk Status Register SYS5ON SYS4ON SYS3ON SYS2ON PLL Modes 29. Timing Requirements for CLKIN1 Devices123 see FigureSYSCLK4 23. PLL2 Block Diagram PLL2 and PLL2 Controller 1 PLL2 Controller Device-Specific Information 31. PLL2 Clock Frequency Ranges1.2 PLL2 Controller Operating Modes Pllref Pllen = 2 PLL2 Controller Memory Map 3 PLL2 Controller Register Descriptions32. PLL2 Controller Registers HEX Address Range Acronym Description PLL Controller Divider 1 Register D1EN 155 ALN1 SYS1 SYS1ON 4 PLL2 Controller Input Clock Electrical Data/Timing 39. Timing Requirements for CLKIN2123 see Figure DDR2 Memory Controller 1 DDR2 Memory Controller Device-Specific Information 3 DDR2 Memory Controller Electrical Data/Timing 2 DDR2 Memory Controller Peripheral Register Descriptions40. DDR2 Memory Controller Registers External Memory Interface a Emifa Emifa Device-Specific Information Emifa Peripheral Register Descriptions 41. Emifa Registers 42. Timing Requirements for Aeclkin for EMIFA12 see Figure Emifa Electrical Data/TimingAeclkin See -33and Figure Aeclkin AECLKOUT1 Setup = Hold = ACEx ABE70ABA10 AED630 Read Data AAOE/ASOE a AAWE/ASWE a AR/W Aardy B Deasserted ABA10 AED630 Strobe Setup = Extended StrobeAeclkout Aardya Asserted Deasserted Setup time, read AEDx valid before Aeclkout high SM320C6455-EP BE1 BE2 BE3 BE4EA1 EA2 EA3 EA4 ASADS/ASRE B AAOE/ASOE B AAWE/ASWEB Write Latency = HOLD/HOLDA Timing HHOLDAL-HOLDL Hold time, Hold low after Holda lowDSP Owns Bus Hold Holda Delay time, Aeclkout high to Abusreq valid AECLKOUTx Busreq Timing 11 I2C Peripheral 11.1 I2C Device-Specific Information I2COAR I2CCLKH I2CSARI2CXSR I2CEMDR 11.2 I2C Peripheral Register Descriptions 51. I2C Registers Standard Mode Fast Mode MIN MAX 11.3 I2C Electrical Data/Timing Stop Start SDA SCLStart Stop 43. I2C Transmit Timings Stop Start Repeated Host-Port Interface HPI Peripheral HPI Device-Specific InformationHPI Peripheral Register Descriptions 54. HPI Control Registers HPI Electrical Data/Timing See -56through Figure NO.PARAMETER HCS Has HCNTL10HR/W Hhwil Hstrobea HD150 HR/W Hhwil Hstrobe a Hrdyb 46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used 48. HPI32 Read Timing has Not Used, Tied High 49. HPI32 Read Timing has Used Has input HCNTL10 Input HR/W input Input HCS input 51. HPI32 Write Timing has Used Input HCS input HD310 input Multichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers McBSP Electrical Data/Timing 720 850 1000/-1000 FIXED-POINT Digital Signal Processor Clkx Clks ClkrClks Master Slave MIN MAX MASTER3 Slave MIN MAXClkx FSX Bit Bitn-1 Master Slave MIN Setup time, DR valid before Clkx high 18PHold time, DR valid after Clkx high + 36P 198 199 Ethernet MAC Emac Ethernet Bus Emac Device-Specific Information Interface Modes Ball Number Device PIN Name 70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii ModesRmii Interface Mode Clocking Emac Peripheral Register Descriptions 71. Ethernet MAC Emac Control Registers Macconfig SoftresetRX6FREEBUFFER RX7FREEBUFFER 72. Emac Statistics Registers HEX Address Range Acronym 74. Emac Descriptor Memory 73. Emac Control Module Registers02C8 2000 02C8 3FFF Emac Descriptor Memory Emac Electrical Data/Timing Mbps Gmii OnlyMrclk Input Mtclk Gmtclk OutputMrclk Input MRXD7−MRXD4GMII only MRXD3−MRXD0 Mtclk Input MTXD7−MTXD4GMII only MTXD3−MTXD0Mtxen Outputs Gmtclk Output Emac Rmii Electrical Data/Timing Rmrefclk Input MRXD1-MRXD0 Mcrsdv Mrxer Inputs 720 1000/-1000 Unit Emac Rgmii Electrical Data/Timing Cycle time, TXC Mbps 40*t cTXC 60*t cTXC 70. Emac Transmit Interface Timing Rgmii OperationAB Mdio Device-Specific Information Management Data Input/Output MdioMdio Peripheral Register Descriptions 89. Mdio Registers Delay time, Mdclk low to Mdio data output valid 100 MdclkMdio input Mdio output Timers Timers Device-Specific InformationTimers Peripheral Register Descriptions 92. Timer 0 Registers 94. Timing Requirements for Timer Inputs1 see Figure Timers Electrical Data/TimingTINPLx TOUTLx Enhanced Viterbi-Decoder Coprocessor VCP2 16.1 VCP2 Device-Specific Information16.2 VCP2 Peripheral Register Descriptions 96. VCP2 Registers Enhanced Turbo Decoder Coprocessor TCP2 17.1 TCP2 Device-Specific InformationTbhd Tbsd 17.2 TCP2 Peripheral Register Descriptions 97. TCP2 Registers 98. Default Values for PCI Configuration Registers Register Default ValuePeripheral Component Interconnect PCI PCI Device-Specific Information 99. PCI Configuration Registers PCI Peripheral Register Descriptions 100. PCI Back End Configuration Registers 101. DSP-toPCI Address Translation Registers 103. PCI External Memory Space 102. PCI Hook Configuration RegistersHEX Address Offset Acronym Register Name 48FF Ffff 49FF Ffff4A7F Ffff 4AFF Ffff PCI Electrical Data/Timing Utopia Device-Specific Information Utopia Peripheral Register Descriptions104. Utopia Registers 105. Utopia Data Queues Receive and Transmit Registers Utopia Electrical Data/Timing 106. Timing Requirements for UXCLK1 see FigureUxclk Urclk UXADDR40 Uxclk UXDATA70Uxclav Uxenb Uxsoc Urclk URDATA70 URADDR40 N Urclav Urenb Ursoc P48 0x1F Serial RapidIO Srio Port Serial RapidIO Device-Specific InformationSerial RapidIO Peripheral Register Descriptions 112. RapidIO Control Registers RIOBLK2EN RIOBLK2ENSTATRIOBLK3EN RIOBLK3ENSTAT RIODOORBELL2ICSR RIODOORBELL2ICCRRIODOORBELL3ICSR RIODOORBELL3ICCR Rioerrrstevnticrr RIOERRRSTEVNTICRR2RIOERRRSTEVNTICRR3 RIOINTDST0DECODE RIOLSU4REG0 RIOLSU4REG1RIOLSU4REG2 RIOLSU4REG3 RIOQUEUE4RXDMAHDP RIOQUEUE5RXDMAHDPRIOQUEUE6RXDMAHDP RIOQUEUE7RXDMAHDP RIORXUMAPL0 RIORXUMAPH0RIORXUMAPL1 RIORXUMAPH1 RapidIO Peripheral-Specific Registers Riolclcfghbar RiolclcfgbarRiobaseid Riohostbaseidlock Rioctrlcapt RiopwtgtidRIOSP0ERRDET RIOSP0RATEEN Serial RapidIO Electrical Data/Timing 245 General-Purpose Input/Output Gpio Gpio Device-Specific InformationGpio Peripheral Register Descriptions 113. Gpio Registers Gpio Electrical Data/Timing 114. Timing Requirements for Gpio Inputs12 see FigurePulse duration, GPOx high 36P 8 Pulse duration, GPOx low 36P 8 Advanced Event Triggering AET Emulation Features and CapabilityTrace Delay time, TCK low to TDO valid Ieee 1149.1 JtagJtag Device-Specific Information 116. Timing Requirements for Jtag Test Port see Figure Revision History C6455 Revision HistorySee ADDITIONS/MODIFICATIONS/DELETIONS Added 0.83 ns C6455-1200 1.2-GHz CPU Cycle Time Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZ Thermal DataPackaging Information AIR Flow MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanQty Page DSP Products ApplicationsRfid