Texas Instruments SM320C6455-EP manual Host-Port Interface HPI Peripheral, HPI Control Registers

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.12 Host-Port Interface (HPI) Peripheral

7.12.1 HPI Device-Specific Information

The C6455 device includes a user-configurable 16 bit or 32 bit Host-port interface (HPI16/HPI32). The AEA14 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16 bit or 32 bit peripheral.

Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the C6455.

An HPI boot is terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0.

7.12.2 HPI Peripheral Register Description(s)

Table 7-54. HPI Control Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME	COMMENTS
0288 0000	-	Reserved
			The CPU has read/write
			access to the
0288 0004	PWREMU_MGMT	HPI power and emulation management register	PWREMU_MGMT register;
			the Host does not have any
			access to this register.
0288 0008 - 0288 0024	-	Reserved
0288 0028	-	Reserved
0288 002C	-	Reserved
			The Host and the CPU have
0288 0030	HPIC	HPI control register	read/write access to the
			HPIC register.(1)

0288 0034	HPIA	HPI address register
	(HPIAW)(2)	(Write)
0288 0038	HPIA	HPI address register
	(HPIAR)(2)	(Read)
0288 000C - 028B 007F	-	Reserved
0288 0080 - 028B FFFF	-	Reserved

The Host has read/write access to the HPIA registers. The CPU has only read access to the HPIA registers.

(1)The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear/acknowledge an interrupt from the host.

(2)There are two 32 bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that HPIAR and HPIAW act as a single 32 bit HPIA (single-HPIA mode) or as two separate 32 bit HPIAs (dual-HPIA mode) from the perspective of the host. The CPU can access HPIAW and HPIAR independently. For details about the HPIA registers and their modes, see the TMS320C645x DSP Host Port Interface (HPI) User's Guide (literature number SPRU969).

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