Texas Instruments SM320C6455-EP manual See -33and Figure, Aeclkin AECLKOUT1

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the

EMIFA Module(1)(2)(3) (see Figure 7-32)

NO.

1 tc(EKO)

2 tw(EKOH)

3 tw(EKOL)

4 tt(EKO)

5td(EKIH-EKOH)

6td(EKIL-EKOL)

	-720
	-850
PARAMETER	A-1000/-1000		UNIT
	-1200
	MIN	MAX
Cycle time, AECLKOUT	E - 0.7	E + 0.7	ns
Pulse duration, AECLKOUT high	EH - 0.7	EH + 0.7	ns
Pulse duration, AECLKOUT low	EL - 0.7	EL + 0.7	ns
Transition time, AECLKOUT		1	ns
Delay time, AECLKIN high to AECLKOUT high	1	8	ns
Delay time, AECLKIN low to AECLKOUT low	1	8	ns

(1)E = the EMIF input clock (AECLKIN or SYSCLK4) period in ns for EMIFA.

(2)The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.

(3)EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA.

AECLKIN

		1
6		3	4	4
5	2

AECLKOUT1

Figure 7-32. AECLKOUT Timing for the EMIFA Module

7.10.3.1Asynchronous Memory Timing

Table 7-44. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module(1)(2)(3)

(see Figure 7-33and Figure 7-34)

NO.

3tsu(EDV-AOEH)

4th(AOEH-EDV)

5tsu(ARDY-EKOH)

6th(EKOH-ARDY)

7 tw(ARDY)

8td(ARDY-HOLD)

9tsu(ARDY-HOLD)

Setup time, AEDx valid before AAOE high

Hold time, AEDx valid after AAOE high

Setup time, AARDY valid before AECLKOUT low

Hold time, AARDY valid after AECLKOUT low

Pulse width, AARDY assertion and deassertion

Delay time, from AARDY sampled deasserted on AECLKOUT falling to beginning of programmed hold period

Setup time, before end of programmed strobe period by which AARDY should be asserted in order to insert extended strobe wait states.

-720 -850

A-1000/-1000 UNIT -1200

MIN MAX

6.5 ns

0	ns
1	ns
2	ns
2E + 5	ns
4E	ns
2E	ns

(1)E = AECLKOUT period in ns for EMIFA

(2)To ensure data setup time, simply program the strobe width wide enough.

(3)AARDY is internally synchronized. To use AARDY as an asynchronous input, the pulse width of the AARDY signal should be at least 2E to ensure setup and hold time is met.

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