Texas Instruments SM320C6455-EP Reset Electrical Data/Timing, 720 1000/-1000 Unit, Parameter

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.6.8Reset Electrical Data/Timing

Table 7-14. Timing Requirements for Reset(1)(2) (3)(see Figure 7-8and Figure 7-9)

NO.

5 tw(POR)

6 tw(RESET)

7tsu(boot)

8th(boot)

Pulse duration, POR low

Pulse duration, RESET low

Setup time, boot mode and configuration pins valid before POR high or RESET high(5)

Hold time, boot mode and configuration pins valid after POR high or RESET high(5)

-720 -850

A-1000/-1000 UNIT -1200

MIN	MAX
256D(4)	ns
24C	ns
6P	ns
6P	ns

(1)C = 1/CLKIN1 clock frequency in ns.

(2)D = 1/CLKIN2 clock frequency in ns.

(3)P = 1/CPU clock frequency in nanoseconds (ns). Note that after power-on reset, warm reset, and max reset the CPU frequency is equal to the CLKIN1 frequency divided by three due to the PLL1 controller being reset (see Section 7.6, Reset Controller).

(4)If CLKIN2 is not used, tw(POR) must be measured in terms of CLKIN1 cycles; otherwise, use CLKIN2 cycles.

(5)AEA[19:0], ABA[1:0], and PCI_EN are the boot configuration pins during device reset. Note: If a configuration pin must be routed out from the device and 3-stated (not driven), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see Section 3.7, Pullup/Pulldown Resistors.

Table 7-15. Switching Characteristics Over Recommended Operating Conditions During Reset(1)

(see Figure 7-9)

			-720
			-850
NO.		PARAMETER	A-1000/-1000		UNIT
			-1200
			MIN	MAX
9	td(PORH-RSTATH)	Delay time, POR high AND RESET high to RESETSTAT high		15000C	ns

(1)C = 1/CLKIN1 clock frequency in ns.

For Figure 7-8, note the following:

∙Z group consists of: all I/O/Z and O/Z pins, except for Low and High group pins. Pins become high impedance as soon as their respective power supply has reached normal operating conditions. Pins remain in high impedance until configured otherwise by their respective peripheral.

∙Low group consists of: UXDATA0/MTXD0/RMTXD0, UXDATA1/MTXD1/RMTXD1, UXDATA2/MTXD2/RMTXD2, UXDATA3/MTXD3/RMTXD3, UXDATA4/MTXD4/RMTXD4, and UXENB/MTXEN/RMTXEN. Pins become low as soon as their respective power supply has reached normal operating conditions. Pins remain low until configured otherwise by their respective peripheral.

∙High group consists of: AHOLD, ABUSREQ, and HRDY/PIRDY. Pins become high as soon as their respective power supply has reached normal operating conditions. Pins remain high until configured otherwise by their respective peripheral. The ABUSREQ pin remains high until the EMIFA is enabled through the PERCFG1 register. Once the EMIFA is enabled, the ABUSREQ pin is driven to its inactive state (driven low).

∙All peripherals must be enable through software following a Power-on Reset; for more details, see Section 7.6.1, Power-on Reset.

∙For power-supply sequence requirements, see Section 7.3.1, Power-Supply Sequencing.

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