Texas Instruments SM320C6455-EP guide

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP

(see Figure 7-52) (continued)

NO.

3 tw(CKRX)

4td(CKRH-FRV)

9td(CKXH-FXV)

12tdis(CKXH-DXHZ)

13td(CKXH-DXV)

14td(FXH-DXV)

PARAMETER

Pulse duration, CLKR/X high or CLKR/X low

Delay time, CLKR high to internal FSR valid

Delay time, CLKX high to internal FSX valid

Disable time, DX high impedance following last data bit from CLKX high

Delay time, CLKX high to DX valid

Delay time, FSX high to DX valid

ONLY applies when in data delay 0 (XDATDLY = 00b) mode

		-720
		-850
		A-1000/-1000			UNIT
		-1200
		MIN		MAX
	CLKR/X int	C – 1(7)		C + 1(7)	ns
	CLKR int	–2.1		3.3	ns
	CLKX int	–1.7		3	ns
	CLKX ext	1.7		9	ns
	CLKX ext	1.7		9
	CLKX int	–3.9		4	ns
	CLKX ext	2.1		9	ns
	CLKX ext	2.1		9
	CLKX int	–3.9 + D1(8)	4	+ D2(8)	ns
	CLKX ext	2.1 + D1(8)	9	+ D2(8)	ns
	CLKX ext	2.1 + D1(8)	9	+ D2(8)
	FSX int	–2.3 + D1(9)	5.6	+ D2(9)
	FSX ext	1.9 + D1(9)	9	+ D2(9)	ns
	FSX ext	1.9 + D1(9)	9	+ D2(9)

(7)C = H or L

S = sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency) S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even L = (CLKGDV + 1)/2 * S if CLKGDV is odd

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see (4) above).

(8)Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 6P, D2 = 12P

(9)Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR. if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 6P, D2 = 12P

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C64x+ Peripheral Information and Electrical Specifications

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Texas Instruments SM320C6455-EP manual FIXED-POINT Digital Signal Processor

Contents

Data Manual Data Manual FIXED-POINT Digital Signal Processor C64x+ Peripheral Information and Electrical Specifications Recommended Operating Conditions FIXED-POINT Digital Signal Processor Enhanced Turbo Decoder Coprocessor TCP2 Features ZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View ZTZ/GTZ BGA Package Bottom ViewDescription Submit Documentation Feedback Functional Block Diagram Functional Block Diagram Hardware Features Device CharacteristicsCharacteristics of the C6455 Processor C6455 CPU DSP Core Description FIXED-POINT Digital Signal Processor C64x+ CPU DSP Core Data Paths Memory Block Description Block Size Bytes HEX Address Range Memory Map SummaryC6455 Memory Map Summary 03FF Ffff 02CF Ffff02DF Ffff 0FFF Ffff Boot Sequence Boot Modes Supported FIXED-POINT Digital Signal Processor 2 2nd-Level Bootloaders Pin Assignments Pin Map C6455 Pin Map Bottom View Quadrant B C6455 Pin Map Bottom View Quadrant C C6455 Pin Map Bottom View Quadrant D Signal Groups Description Gpio TINPL1 TOUTL1TINPL0 URADDR4/PCBE0/GP2C SYSCLK4/GP1A ACE2A ACE5A ACE4AACE3A ABE7 ABE6 ABE5 ABE4 CLKR1/GP0 HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 onlyHpia Clks Shared UXADDR4/MDCLK UXADDR3/MDIORgmdio URSOC/MRXER/RMRXER UXDATA1/MTXD1/RMTXD1 UXDATA4/MTXD4URDATA3/MRXD3 UXDATA3/MTXD3 URDATA2/MRXD2 UXDATA2/MTXD2 UXDATA0/MTXD0/RMTXD0 Terminal Functions SignalIPD/IPU Description Name CLOCK/PLL Configurations Terminal Functions Signal Name Type 1 IPD/IPU Emifa 64 BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control Emifa 64 BIT Control Signals Common to ALL Types of MemoryEmifa 64 BIT BUS Arbitration AEA1916 Signal TYPE1 NameIPD/IPU2 Description Emifa 64 BIT Address AEA15 AEA5 IPD/IPU Description NameAEA6 AEA4 Signal TYPE1 IPD/IPU2 Description Name Emifa 64 BIT Data AED19 AED21AED20 AED18 IPD/IPU2 Description DDR2 Memory Controller 32 BIT Address INTER-INTEGRATED Circuit I2C TimerIPD/IPU Description Name DDR2 Memory Controller 32 BIT Data Multichannel Buffered Serial Port 0 McBSP0 Signal TYPE1 IPD/IPU2 Description NameMultichannel Buffered Serial Port 1 McBSP1 Utopia Slave ATM Controller Transmit Interface Utopia Slave ATM Controller Receive Interface URADDR2/PINTA1/ GP14 URADDR1/PRSTTYPE1 IPD/IPU2 Description Management Data INPUT/OUTPUT Mdio for Rgmii Signal TYPE1 IPD/IPU2 Description Name Rapidio Serial PortManagement Data INPUT/OUTPUT Mdio for MII/RMII/GMII Device Configuration RSV07 RSV09 RgrefclkRSV05 Reserved for Test RSV15 RSV13RSV14 RSV16 Supply Voltage Pins Signal TYPE1 Name noIPD/IPU2 Description Supply Voltage Monitor Pins U16 AC6 AC9 AA1 AA6AB7 AF1 AD5 AD7AE6 AE8 CV DD GND Ground PinsCvdd F20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AC7 AC8 AA2 AA7AB6 GND AF2 AD6AE4 AE7 AH1 Device Support DevelopmentDevelopment Support Device and Development-Support Tool Nomenclature SM=Qualifieddevice C6000 DSP platforms FIXED-POINT Digital Signal Processor Configuration IPD PIN Device Configuration at Device ResetC6455 Device Configuration Pins AEA190, ABA10, and Pcien IPU1 AEA12 AEA14AEA13 AEA11 IPU Peripheral Configuration at Device ResetConfiguration IPD Functional Description PIN ABA0 Lower Upper Configuration PIN Setting Utopiaen Pcien PINUTOPIAEN, and MACSEL10 Peripheral Selection Utopia and Emac AUTO-INIT State Peripheral Selection After Device ResetPeripheral States Peripherals That can be This State Static Powerdown Reset Enable Progress Disabled Enabled Unlock the PERCFG0 register by Using the Perlock register HEX Address Range Acronym Register Name Device State Control RegistersDevice State Control Registers Bit Field Value Description 310 Peripheral Lock Register DescriptionLockval Lockval Peripheral Configuration Register 0 Description Bit Field Value Description Bit Field DDR2CTL Peripheral Configuration Register 1 DescriptionDDR2CTL Emifactl I2CSTAT Peripheral Status Registers DescriptionHpistat 1715 Utopiastat SM320C6455-EPUtopiastat Pcistat Emac Configuration Register Emaccfg Description Rmiirst Emulator Buffer Powerdown Register Emubufpd Description Emuctl Sysclkout MCBSP1EN PCI66 Device Status Register DescriptionEmifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0 Pcieeai MACSEL1 MACSEL0 Utopiaen PcieeaiMACSEL10 Variant Part Number Manufacturer LSB BOOTMODE30Jtag ID Jtagid Register Description Variant Configuration Examples Pullup/Pulldown Resistors HPI VCP2 HRDY,HINT FIXED-POINT Digital Signal Processor Internal Buses, Bridges, and Switch Fabrics System Interconnect Data Switch Fabric Connections Switched Central Resource Block Diagram Configuration Switch Fabric SCR Connection Matrix C64x+ Megamodule SCR Connection Bus Priorities C6455 Default Bus Master PrioritiesBUS Master Default Priority Control Priority Level X+ Megamodule Block Diagram Memory Architecture C6455 L1P Memory Configurations C6455 L2 Memory Configurations Available Memory Page Protection Schemes Memory ProtectionBandwidth Management AID0 Bit Megamodule Reset Global or Local Power-Down ControlMegamodule Resets Reset Type Megamodule Version Megamodule RevisionVersion Revision a Revision C64x+ Megamodule Register Descriptions Megamodule Interrupt Registers Megamodule Idma Registers Megamodule Powerdown Control RegistersMegamodule Revision Register Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA6 L2MPPA4L2MPPA5 L2MPPA7 L1PMPPA20 L1PMPPA18L1PMPPA19 L1PMPPA21 HEX Address Range Acronym Register Name Comments 11. Device Configuration Registers Chip-Level Registers10. CPU Megamodule Bandwidth Management Registers MIN NOM MAX Unit Recommended Operating ConditionsDV DD12, DV DDRM, AV DDT, AV DDA AV DDA VOS Recommended Operating ConditionsVSS VIH VIL TDO DVDD33 = MIN IOH = MAX Parameter Test CONDITIONS1 MIN TYP MAX UnitVOH VOL DVDD33 = MIN IOL = MAX Current DC Parameter Information 1 3.3-V Signal Transition Levels2 3.3-V Signal Transition Rates Timing Parameters and Board Routing Analysis Power-Supply Sequencing Recommended Clock and Control Signal Transition BehaviorPower Supplies Power-Supply Decoupling 108 Enhanced Direct Memory Access EDMA3 Controller C6455 EDMA3 Channel Synchronization Events1 EDMA3 Device-Specific InformationEDMA3 Channel Synchronization Events Edma Binary Event Name Event Description Channel EDMA3 Channel Controller Registers EDMA3 Peripheral Register DescriptionsC6455 EDMA3 Channel Synchronization Events DCHMAP10 DCHMAP8DCHMAP9 DCHMAP11 DCHMAP57 DCHMAP55DCHMAP56 DCHMAP58 DRAE6 DRAE5DRAEH5 DRAEH6 QSTAT2 QSTAT0QSTAT1 QSTAT3 Shadow Region 0 Channel Registers Interrupt Enable Register High EDMA3 Parameter RAM1 EDMA3 Transfer Controller 0 Registers EDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 121 EDMA3 Transfer Controller 3 Registers 123 10. C6455 System Event Mapping InterruptsInterrupt Sources and Interrupt Controller Event Number Interrupt Event Description XINT1 XINT0RINT1 TINTLO0 L1PCMPA L1PED1Pdcint L1PDMPA NMI External Interrupts Electrical Data/Timing11. Timing Requirements for External Interrupts1 see Figure 12. Reset Types Reset ControllerPower-on Reset POR Pin Type Initiator Warm Reset Reset Pin CPU Reset Max ResetSystem Reset Reset Priority Srst Mrst Wrst POR Reset Controller RegisterReset Type Status Register Description Srst 720 1000/-1000 Unit Reset Electrical Data/Timing14. Timing Requirements for Reset12 3see -8and Figure Parameter Power-Up Timing Resetstat CLKIN1 CLKIN2 POR PLL1 and PLL1 Controller 1 PLL1 Controller Device-Specific Information Internal Clocks and Maximum Operating Frequencies 16. PLL1 Clock Frequency Ranges 1.3 PLL1 Stabilization, Lock, and Reset TimesClock Signal MIN MAX Unit 1.2 PLL1 Controller Operating Modes 2 PLL1 Controller Memory Map 17. PLL1 Stabilization, Lock, and Reset Times18. PLL1 Controller Registers Including Reset Controller MIN TYP Pllrst 3 PLL1 Controller Register Descriptions3.1 PLL1 Control Register Pllpwrdn PLL Multiplier Control Register 20. PLL Multiplier Control Register Pllm Field Descriptions Ratio PLL Pre-Divider Control RegisterPreden PLL Controller Divider 4 Register D4EN PLL Controller Divider 5 Register D5EN PLL Controller Command Register Goset PLL Controller Status Register Gostat PLL Controller Clock Align Control Register SYS5 Plldiv Ratio Change Status RegisterSYS5 SYS4 Sysclk Status Register SYS5ON SYS4ON SYS3ON SYS2ON SYSCLK4 29. Timing Requirements for CLKIN1 Devices123 see FigurePLL Modes 23. PLL2 Block Diagram PLL2 and PLL2 Controller 1.2 PLL2 Controller Operating Modes 1 PLL2 Controller Device-Specific Information31. PLL2 Clock Frequency Ranges Pllref Pllen = 32. PLL2 Controller Registers 2 PLL2 Controller Memory Map3 PLL2 Controller Register Descriptions HEX Address Range Acronym Description PLL Controller Divider 1 Register D1EN 155 ALN1 SYS1 SYS1ON 4 PLL2 Controller Input Clock Electrical Data/Timing 39. Timing Requirements for CLKIN2123 see Figure DDR2 Memory Controller 1 DDR2 Memory Controller Device-Specific Information 40. DDR2 Memory Controller Registers 2 DDR2 Memory Controller Peripheral Register Descriptions3 DDR2 Memory Controller Electrical Data/Timing External Memory Interface a Emifa Emifa Device-Specific Information Emifa Peripheral Register Descriptions 41. Emifa Registers Aeclkin Emifa Electrical Data/Timing42. Timing Requirements for Aeclkin for EMIFA12 see Figure See -33and Figure Aeclkin AECLKOUT1 ABA10 AED630 Read Data Setup = Hold =ACEx ABE70 AAOE/ASOE a AAWE/ASWE a AR/W Aardy B Deasserted Aeclkout Aardya Asserted Deasserted Strobe Setup = Extended StrobeABA10 AED630 Setup time, read AEDx valid before Aeclkout high EA1 EA2 EA3 EA4 SM320C6455-EPBE1 BE2 BE3 BE4 ASADS/ASRE B AAOE/ASOE B AAWE/ASWEB Write Latency = DSP Owns Bus HOLD/HOLDA TimingHHOLDAL-HOLDL Hold time, Hold low after Holda low Hold Holda Delay time, Aeclkout high to Abusreq valid AECLKOUTx Busreq Timing 11 I2C Peripheral 11.1 I2C Device-Specific Information I2CXSR I2COARI2CCLKH I2CSAR I2CEMDR 11.2 I2C Peripheral Register Descriptions 51. I2C Registers Standard Mode Fast Mode MIN MAX 11.3 I2C Electrical Data/Timing Start Stop SDA SCLStop Start 43. I2C Transmit Timings Stop Start Repeated HPI Peripheral Register Descriptions Host-Port Interface HPI PeripheralHPI Device-Specific Information 54. HPI Control Registers HPI Electrical Data/Timing See -56through Figure NO.PARAMETER HR/W Hhwil Hstrobea HCS HasHCNTL10 HD150 HR/W Hhwil Hstrobe a Hrdyb 46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used 48. HPI32 Read Timing has Not Used, Tied High 49. HPI32 Read Timing has Used Has input HCNTL10 Input HR/W input Input HCS input 51. HPI32 Write Timing has Used Input HCS input HD310 input Multichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers McBSP Electrical Data/Timing 720 850 1000/-1000 FIXED-POINT Digital Signal Processor Clks Clks ClkrClkx Clkx FSX Master Slave MIN MAXMASTER3 Slave MIN MAX Bit Bitn-1 Hold time, DR valid after Clkx high + 36P Setup time, DR valid before Clkx high 18PMaster Slave MIN 198 199 Ethernet MAC Emac Ethernet Bus Emac Device-Specific Information Interface Modes Rmii 70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii ModesBall Number Device PIN Name Interface Mode Clocking Emac Peripheral Register Descriptions 71. Ethernet MAC Emac Control Registers RX6FREEBUFFER MacconfigSoftreset RX7FREEBUFFER 72. Emac Statistics Registers HEX Address Range Acronym 02C8 2000 02C8 3FFF Emac Descriptor Memory 73. Emac Control Module Registers74. Emac Descriptor Memory Mrclk Input Emac Electrical Data/TimingMbps Gmii Only Mtclk Mrclk Input MRXD7−MRXD4GMII only GmtclkOutput MRXD3−MRXD0 Mtxen Outputs Mtclk Input MTXD7−MTXD4GMII onlyMTXD3−MTXD0 Gmtclk Output Emac Rmii Electrical Data/Timing Rmrefclk Input MRXD1-MRXD0 Mcrsdv Mrxer Inputs 720 1000/-1000 Unit Emac Rgmii Electrical Data/Timing Cycle time, TXC Mbps 40*t cTXC 60*t cTXC 70. Emac Transmit Interface Timing Rgmii OperationAB Mdio Peripheral Register Descriptions 89. Mdio Registers Management Data Input/Output MdioMdio Device-Specific Information Mdio input Delay time, Mdclk low to Mdio data output valid 100Mdclk Mdio output Timers Peripheral Register Descriptions TimersTimers Device-Specific Information 92. Timer 0 Registers TINPLx TOUTLx Timers Electrical Data/Timing94. Timing Requirements for Timer Inputs1 see Figure 16.2 VCP2 Peripheral Register Descriptions Enhanced Viterbi-Decoder Coprocessor VCP216.1 VCP2 Device-Specific Information 96. VCP2 Registers Tbhd Enhanced Turbo Decoder Coprocessor TCP217.1 TCP2 Device-Specific Information Tbsd 17.2 TCP2 Peripheral Register Descriptions 97. TCP2 Registers Peripheral Component Interconnect PCI 98. Default Values for PCI Configuration RegistersRegister Default Value PCI Device-Specific Information 99. PCI Configuration Registers PCI Peripheral Register Descriptions 100. PCI Back End Configuration Registers 101. DSP-toPCI Address Translation Registers HEX Address Offset Acronym Register Name 102. PCI Hook Configuration Registers103. PCI External Memory Space 4A7F Ffff 48FF Ffff49FF Ffff 4AFF Ffff PCI Electrical Data/Timing 104. Utopia Registers Utopia Device-Specific InformationUtopia Peripheral Register Descriptions 105. Utopia Data Queues Receive and Transmit Registers Uxclk Utopia Electrical Data/Timing106. Timing Requirements for UXCLK1 see Figure Urclk Uxclav Uxenb Uxsoc Uxclk UXDATA70UXADDR40 Urclk URDATA70 URADDR40 N Urclav Urenb Ursoc P48 0x1F Serial RapidIO Peripheral Register Descriptions Serial RapidIO Srio PortSerial RapidIO Device-Specific Information 112. RapidIO Control Registers RIOBLK3EN RIOBLK2ENRIOBLK2ENSTAT RIOBLK3ENSTAT RIODOORBELL3ICSR RIODOORBELL2ICSRRIODOORBELL2ICCR RIODOORBELL3ICCR RIOERRRSTEVNTICRR3 RioerrrstevnticrrRIOERRRSTEVNTICRR2 RIOINTDST0DECODE RIOLSU4REG2 RIOLSU4REG0RIOLSU4REG1 RIOLSU4REG3 RIOQUEUE6RXDMAHDP RIOQUEUE4RXDMAHDPRIOQUEUE5RXDMAHDP RIOQUEUE7RXDMAHDP RIORXUMAPL1 RIORXUMAPL0RIORXUMAPH0 RIORXUMAPH1 RapidIO Peripheral-Specific Registers Riobaseid RiolclcfghbarRiolclcfgbar Riohostbaseidlock RIOSP0ERRDET RioctrlcaptRiopwtgtid RIOSP0RATEEN Serial RapidIO Electrical Data/Timing 245 Gpio Peripheral Register Descriptions General-Purpose Input/Output GpioGpio Device-Specific Information 113. Gpio Registers Pulse duration, GPOx high 36P 8 Gpio Electrical Data/Timing114. Timing Requirements for Gpio Inputs12 see Figure Pulse duration, GPOx low 36P 8 Trace Emulation Features and CapabilityAdvanced Event Triggering AET Jtag Device-Specific Information Delay time, TCK low to TDO validIeee 1149.1 Jtag 116. Timing Requirements for Jtag Test Port see Figure See ADDITIONS/MODIFICATIONS/DELETIONS Revision HistoryC6455 Revision History Added 0.83 ns C6455-1200 1.2-GHz CPU Cycle Time Packaging Information Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZThermal Data AIR Flow Qty Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Page Rfid Products ApplicationsDSP