Texas Instruments SM320C6455-EP Master Slave MIN MAX, MASTER3 Slave MIN MAX, Clkx FSX, Bit Bitn-1

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

Table 7-62. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0(1)(2)

(see Figure 7-54)

				-720
				-850
NO.				A-1000/-1000		UNIT
				-1200
			MASTER		SLAVE
			MIN	MAX	MIN	MAX
4	tsu(DRV-CKXL)	Setup time, DR valid before CLKX low	12		2 – 18P	ns
5	th(CKXL-DRV)	Hold time, DR valid after CLKX low	4		5 + 36P	ns

(1)P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2)For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

Table 7-63. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI

Master or Slave: CLKSTP = 10b, CLKXP = 0(1)(2) (see Figure 7-54)

NO.

1th(CKXL-FXL)

2td(FXL-CKXH)

3td(CKXH-DXV)

6tdis(CKXL-DXHZ)

7tdis(FXH-DXHZ)

8td(FXL-DXV)

PARAMETER

Hold time, FSX low after CLKX low(4) Delay time, FSX low to CLKX high(5)

Delay time, CLKX high to DX valid

Disable time, DX high impedance following last data bit from CLKX low

Disable time, DX high impedance following last data bit from FSX high

Delay time, FSX low to DX valid

		-720
		-850
	A-1000/-1000			UNIT
		-1200
MASTER(3)		SLAVE
MIN	MAX	MIN	MAX
T – 2	T + 3			ns
L – 2	L + 3			ns
–2	4	18P + 2.8	30P + 17	ns
L – 2	L + 3			ns
		6P + 3	18P + 17	ns
		12P + 2	24P + 17	ns

(1)P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2)For all SPI Slave modes, CLKG is programmed as 1/6 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3)S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency) S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period) T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even H = (CLKGDV + 1)/2 * S if CLKGDV is odd

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even L = (CLKGDV + 1)/2 * S if CLKGDV is odd

(4)FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5)FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock (CLKX).

CLKX
	1	2
FSX
	7	8
	6		3
DX	Bit 0	Bit(n-1)	(n-2)	(n-3)	(n-4)
		4	5
DR	Bit 0	Bit(n-1)	(n-2)	(n-3)	(n-4)

Figure 7-54. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

196 C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback