Texas Instruments SM320C6455-EP manual Recommended Operating Conditions

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

6.2 Recommended Operating Conditions 101

6.3Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case

Temperature (Unless Otherwise Noted) 103

7	C64x+ Peripheral Information and Electrical Specifications				105
	7.1	Parameter Information			105
		7.1.1	3.3-V Signal Transition Levels		105
		7.1.2	3.3-V Signal Transition Rates		105
		7.1.3	Timing Parameters and Board Routing Analysis		106
	7.2	Recommended Clock and Control Signal Transition Behavior			107
	7.3	Power Supplies			107
		7.3.1	Power-Supply Sequencing		107
		7.3.2	Power-Supply Decoupling		107
		7.3.3	Power-Down Operation		107
		7.3.4	Preserving Boundary-Scan Functionality on RGMII and DDR2 Memory Pins		108
	7.4	Enhanced Direct Memory Access (EDMA3) Controller			109
		7.4.1	EDMA3 Device-Specific Information		110
		7.4.2	EDMA3 Channel Synchronization Events		110
		7.4.3	EDMA3 Peripheral Register Description(s)		111
	7.5	Interrupts			124
		7.5.1	Interrupt Sources and Interrupt Controller		124
		7.5.2	External Interrupts Electrical Data/Timing		127
	7.6	Reset Controller			128
		7.6.1	Power-on Reset (POR Pin)		128
		7.6.2	Warm Reset (RESET Pin)		129
		7.6.3	Max Reset		130
		7.6.4	System Reset		130
		7.6.5	CPU Reset		130
		7.6.6	Reset Priority		131
		7.6.7	Reset Controller Register		132
			7.6.7.1 Reset Type Status Register Description		132
		7.6.8	Reset Electrical Data/Timing		133
	7.7	PLL1 and PLL1 Controller			136
		7.7.1	PLL1 Controller Device-Specific Information		137
			7.7.1.1 Internal Clocks and Maximum Operating Frequencies		137
			7.7.1.2 PLL1 Controller Operating Modes		138
			7.7.1.3 PLL1 Stabilization, Lock, and Reset Times		138
		7.7.2	PLL1 Controller Memory Map		139
		7.7.3	PLL1 Controller Register Descriptions		140
			7.7.3.1	PLL1 Control Register	140
			7.7.3.2 PLL Multiplier Control Register		141
			7.7.3.3 PLL Pre-Divider Control Register		142
			7.7.3.4 PLL Controller Divider 4 Register		143
			7.7.3.5 PLL Controller Divider 5 Register		144
			7.7.3.6 PLL Controller Command Register		145
			7.7.3.7 PLL Controller Status Register		146
			7.7.3.8 PLL Controller Clock Align Control Register		147
			7.7.3.9 PLLDIV Ratio Change Status Register		148
			7.7.3.10	SYSCLK Status Register	149
		7.7.4	PLL1 Controller Input and Output Clock Electrical Data/Timing		150
	7.8	PLL2 and PLL2 Controller			151
		7.8.1	PLL2 Controller Device-Specific Information		152
			7.8.1.1 Internal Clocks and Maximum Operating Frequencies		152
			7.8.1.2 PLL2 Controller Operating Modes		152

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