Texas Instruments SM320C6455-EP System Interconnect, Internal Buses, Bridges, and Switch Fabrics

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

4 System Interconnect

On the C6455 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers between master peripherals and slave peripherals. Through a switch fabric the CPU can send data to the Viterbi co-processor (VCP2) without affecting a data transfer between the PCI and the DDR2 memory controller. The switch fabrics also allow for seamless arbitration between the system masters when accessing system slaves.

4.1Internal Buses, Bridges, and Switch Fabrics

Two types of buses exist in the C6455 device: data buses and configuration buses. Some C6455 peripherals have both a data bus and a configuration bus interface, while others only have one type of interface. Furthermore, the bus interface width and speed varies from peripheral to peripheral.

Configuration buses are mainly used to access the register space of a peripheral and the data buses are used mainly for data transfers. However, in some cases, the configuration bus is also used to transfer data. For example, data is transferred to the VCP2 and TCP2 configuration bus. Similarly, the data bus can also be used to access the register space of a peripheral. For example, the EMIFA and DDR2 memory controller registers are accessed through their data bus interface.

The C64x+ Megamodule, the EDMA3 traffic controllers, and the various system peripherals can be classified into two categories: masters and slaves. Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves on the other hand rely on the EDMA3 to perform transfers to and from them. Masters include the EDMA3 traffic controllers, SRIO, and PCI. Slaves include the McBSP, UTOPIA, and I2C.

The C6455 device contains two switch fabrics through which masters and slaves communicate. The data switch fabric, known as the data switched central resource (SCR), is a high-throughput interconnect mainly used to move data across the system (for more information, see Section 4.2). The data SCR connects masters to slaves via 128 bit data buses running at a SYSCLK2 frequency (SYSCLK2 is generated from PLL1 controller). Peripherals that have a 128 bit data bus interface running at this speed can connect directly to the data SCR; other peripherals require a bridge.

The configuration switch fabric, also known as the configuration switch central resource (SCR) is mainly used by the C64x+ Megamodule to access peripheral registers (for more information, see Section 4.3). The configuration SCR connects C64x+ Megamodule to slaves via 32 bit configuration buses running at a SYSCLK2 frequency (SYSCLK2 is generated from PLL1 controller). As with the data SCR, some peripherals require the use of a bridge to interface to the configuration SCR. Note that the data SCR also connects to the configuration SCR.

Bridges perform a variety of functions:

∙Conversion between configuration bus and data bus.

∙Width conversion between peripheral bus width and SCR bus width.

∙Frequency conversion between peripheral bus frequency and SCR bus frequency.

For example, the EMIFA and DDR2 memory controller require a bridge to convert their 64 bit data bus interface into a 128 bit interface so that they can connect to the data SCR. In the case of the TCP2 and VCP2, a bridge is required to connect the data SCR to the 64-bit configuration bus interface.

Note that some peripherals can be accessed through the data SCR and also through the configuration SCR.

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