155 | Texas Instruments SM320C6455-EP manual

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.8.3.2 PLL Controller Command Register

The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-25and described in Table 7-34.

31					16
			Reserved
			R-0
15			2	1	0
			Reserved	Rsvd	GOSET
			R-0	R/W-0	R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
	Figure 7-25. PLL Controller Command Register (PLLCMD) [Hex Address: 029C 0138]
	Table 7-34. PLL Controller Command Register (PLLCMD) Field Descriptions
Bit	Field	Value	Description
31:2	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
1	Reserved		Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0	GOSET		GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1
			to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous
			GO operations have completed.
		0	No effect. Write of 0 clears bit to 0.

1Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further writes of 1 can initiate the GO operation.

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C64x+ Peripheral Information and Electrical Specifications

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Texas Instruments SM320C6455-EP manual 155

Contents

Data Manual Data Manual FIXED-POINT Digital Signal Processor Recommended Operating Conditions C64x+ Peripheral Information and Electrical Specifications FIXED-POINT Digital Signal Processor Enhanced Turbo Decoder Coprocessor TCP2 Features ZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View ZTZ/GTZ BGA Package Bottom ViewDescription Submit Documentation Feedback Functional Block Diagram Functional Block Diagram C6455 Device CharacteristicsCharacteristics of the C6455 Processor Hardware Features CPU DSP Core Description FIXED-POINT Digital Signal Processor C64x+ CPU DSP Core Data Paths Memory Block Description Block Size Bytes HEX Address Range Memory Map SummaryC6455 Memory Map Summary 0FFF Ffff 02CF Ffff02DF Ffff 03FF Ffff Boot Modes Supported Boot Sequence FIXED-POINT Digital Signal Processor 2 2nd-Level Bootloaders Pin Map Pin Assignments C6455 Pin Map Bottom View Quadrant B C6455 Pin Map Bottom View Quadrant C C6455 Pin Map Bottom View Quadrant D Signal Groups Description URADDR4/PCBE0/GP2C SYSCLK4/GP1A TINPL1 TOUTL1TINPL0 Gpio ABE7 ABE6 ABE5 ABE4 ACE5A ACE4AACE3A ACE2A Clks Shared HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 onlyHpia CLKR1/GP0 URSOC/MRXER/RMRXER UXADDR3/MDIORgmdio UXADDR4/MDCLK UXDATA0/MTXD0/RMTXD0 UXDATA4/MTXD4URDATA3/MRXD3 UXDATA3/MTXD3 URDATA2/MRXD2 UXDATA2/MTXD2 UXDATA1/MTXD1/RMTXD1 Terminal Functions SignalIPD/IPU Description Name CLOCK/PLL Configurations Terminal Functions Signal Name Type 1 IPD/IPU Emifa 64 BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control Emifa 64 BIT Control Signals Common to ALL Types of MemoryEmifa 64 BIT BUS Arbitration AEA15 Signal TYPE1 NameIPD/IPU2 Description Emifa 64 BIT Address AEA1916 AEA4 IPD/IPU Description NameAEA6 AEA5 Signal TYPE1 IPD/IPU2 Description Name Emifa 64 BIT Data AED18 AED21AED20 AED19 DDR2 Memory Controller 32 BIT Address IPD/IPU2 Description INTER-INTEGRATED Circuit I2C TimerIPD/IPU Description Name DDR2 Memory Controller 32 BIT Data Utopia Slave ATM Controller Transmit Interface Signal TYPE1 IPD/IPU2 Description NameMultichannel Buffered Serial Port 1 McBSP1 Multichannel Buffered Serial Port 0 McBSP0 Utopia Slave ATM Controller Receive Interface URADDR2/PINTA1/ GP14 URADDR1/PRSTTYPE1 IPD/IPU2 Description Management Data INPUT/OUTPUT Mdio for Rgmii Signal TYPE1 IPD/IPU2 Description Name Rapidio Serial PortManagement Data INPUT/OUTPUT Mdio for MII/RMII/GMII Device Configuration Reserved for Test RgrefclkRSV05 RSV07 RSV09 RSV16 RSV13RSV14 RSV15 Supply Voltage Pins Signal TYPE1 Name noIPD/IPU2 Description Supply Voltage Monitor Pins U16 AC6 AC9 AA1 AA6AB7 CV DD AD5 AD7AE6 AE8 AF1 GND Ground PinsCvdd F20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AC7 AC8 AA2 AA7AB6 AH1 AD6AE4 AE7 GND AF2 Device and Development-Support Tool Nomenclature DevelopmentDevelopment Support Device Support SM=Qualifieddevice C6000 DSP platforms FIXED-POINT Digital Signal Processor IPU1 Device Configuration at Device ResetC6455 Device Configuration Pins AEA190, ABA10, and Pcien Configuration IPD PIN AEA11 AEA14AEA13 AEA12 ABA0 Peripheral Configuration at Device ResetConfiguration IPD Functional Description PIN IPU AUTO-INIT Configuration PIN Setting Utopiaen Pcien PINUTOPIAEN, and MACSEL10 Peripheral Selection Utopia and Emac Lower Upper Peripherals That can be This State Peripheral Selection After Device ResetPeripheral States State Unlock the PERCFG0 register by Using the Perlock register Static Powerdown Reset Enable Progress Disabled Enabled HEX Address Range Acronym Register Name Device State Control RegistersDevice State Control Registers Lockval Peripheral Lock Register DescriptionLockval Bit Field Value Description 310 Bit Field Value Description Peripheral Configuration Register 0 Description Bit Field DDR2CTL Peripheral Configuration Register 1 DescriptionDDR2CTL Emifactl I2CSTAT Peripheral Status Registers DescriptionHpistat 1715 Utopiastat SM320C6455-EPUtopiastat Pcistat Rmiirst Emac Configuration Register Emaccfg Description Emuctl Emulator Buffer Powerdown Register Emubufpd Description Pcieeai MACSEL1 MACSEL0 Device Status Register DescriptionEmifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0 Sysclkout MCBSP1EN PCI66 Utopiaen PcieeaiMACSEL10 Variant BOOTMODE30Jtag ID Jtagid Register Description Variant Part Number Manufacturer LSB Pullup/Pulldown Resistors Configuration Examples HPI VCP2 HRDY,HINT FIXED-POINT Digital Signal Processor System Interconnect Internal Buses, Bridges, and Switch Fabrics Data Switch Fabric Connections Switched Central Resource Block Diagram SCR Connection Matrix Configuration Switch Fabric C64x+ Megamodule SCR Connection Bus Priorities C6455 Default Bus Master PrioritiesBUS Master Default Priority Control Priority Level Memory Architecture X+ Megamodule Block Diagram C6455 L1P Memory Configurations C6455 L2 Memory Configurations AID0 Bit Memory ProtectionBandwidth Management Available Memory Page Protection Schemes Reset Type Megamodule Power-Down ControlMegamodule Resets Megamodule Reset Global or Local Revision Megamodule RevisionVersion Revision a Version Megamodule Interrupt Registers C64x+ Megamodule Register Descriptions Megamodule Idma Registers Megamodule Powerdown Control RegistersMegamodule Revision Register Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA7 L2MPPA4L2MPPA5 L2MPPA6 L1PMPPA21 L1PMPPA18L1PMPPA19 L1PMPPA20 HEX Address Range Acronym Register Name Comments 11. Device Configuration Registers Chip-Level Registers10. CPU Megamodule Bandwidth Management Registers AV DDA Recommended Operating ConditionsDV DD12, DV DDRM, AV DDT, AV DDA MIN NOM MAX Unit VOS Recommended Operating ConditionsVSS VIH VIL DVDD33 = MIN IOL = MAX Parameter Test CONDITIONS1 MIN TYP MAX UnitVOH VOL TDO DVDD33 = MIN IOH = MAX Current DC Parameter Information 1 3.3-V Signal Transition Levels2 3.3-V Signal Transition Rates Timing Parameters and Board Routing Analysis Power-Supply Decoupling Recommended Clock and Control Signal Transition BehaviorPower Supplies Power-Supply Sequencing 108 Enhanced Direct Memory Access EDMA3 Controller Edma Binary Event Name Event Description Channel EDMA3 Device-Specific InformationEDMA3 Channel Synchronization Events C6455 EDMA3 Channel Synchronization Events1 EDMA3 Channel Controller Registers EDMA3 Peripheral Register DescriptionsC6455 EDMA3 Channel Synchronization Events DCHMAP11 DCHMAP8DCHMAP9 DCHMAP10 DCHMAP58 DCHMAP55DCHMAP56 DCHMAP57 DRAEH6 DRAE5DRAEH5 DRAE6 QSTAT3 QSTAT0QSTAT1 QSTAT2 Shadow Region 0 Channel Registers Interrupt Enable Register High EDMA3 Transfer Controller 0 Registers EDMA3 Parameter RAM1 EDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 121 EDMA3 Transfer Controller 3 Registers 123 Event Number Interrupt Event Description InterruptsInterrupt Sources and Interrupt Controller 10. C6455 System Event Mapping TINTLO0 XINT0RINT1 XINT1 L1PDMPA L1PED1Pdcint L1PCMPA NMI External Interrupts Electrical Data/Timing11. Timing Requirements for External Interrupts1 see Figure Type Initiator Reset ControllerPower-on Reset POR Pin 12. Reset Types Warm Reset Reset Pin CPU Reset Max ResetSystem Reset Reset Priority Srst Reset Controller RegisterReset Type Status Register Description Srst Mrst Wrst POR Parameter Reset Electrical Data/Timing14. Timing Requirements for Reset12 3see -8and Figure 720 1000/-1000 Unit Power-Up Timing CLKIN1 CLKIN2 POR Resetstat PLL1 and PLL1 Controller Internal Clocks and Maximum Operating Frequencies 1 PLL1 Controller Device-Specific Information 1.2 PLL1 Controller Operating Modes 1.3 PLL1 Stabilization, Lock, and Reset TimesClock Signal MIN MAX Unit 16. PLL1 Clock Frequency Ranges MIN TYP 17. PLL1 Stabilization, Lock, and Reset Times18. PLL1 Controller Registers Including Reset Controller 2 PLL1 Controller Memory Map Pllpwrdn 3 PLL1 Controller Register Descriptions3.1 PLL1 Control Register Pllrst 20. PLL Multiplier Control Register Pllm Field Descriptions PLL Multiplier Control Register Ratio PLL Pre-Divider Control RegisterPreden D4EN PLL Controller Divider 4 Register D5EN PLL Controller Divider 5 Register Goset PLL Controller Command Register Gostat PLL Controller Status Register PLL Controller Clock Align Control Register SYS5 Plldiv Ratio Change Status RegisterSYS5 SYS4 SYS5ON SYS4ON SYS3ON SYS2ON Sysclk Status Register SYSCLK4 29. Timing Requirements for CLKIN1 Devices123 see FigurePLL Modes PLL2 and PLL2 Controller 23. PLL2 Block Diagram Pllref Pllen = 1 PLL2 Controller Device-Specific Information31. PLL2 Clock Frequency Ranges 1.2 PLL2 Controller Operating Modes HEX Address Range Acronym Description 2 PLL2 Controller Memory Map3 PLL2 Controller Register Descriptions 32. PLL2 Controller Registers D1EN PLL Controller Divider 1 Register 155 ALN1 SYS1 SYS1ON 39. Timing Requirements for CLKIN2123 see Figure 4 PLL2 Controller Input Clock Electrical Data/Timing 1 DDR2 Memory Controller Device-Specific Information DDR2 Memory Controller 40. DDR2 Memory Controller Registers 2 DDR2 Memory Controller Peripheral Register Descriptions3 DDR2 Memory Controller Electrical Data/Timing Emifa Device-Specific Information External Memory Interface a Emifa 41. Emifa Registers Emifa Peripheral Register Descriptions Aeclkin Emifa Electrical Data/Timing42. Timing Requirements for Aeclkin for EMIFA12 see Figure Aeclkin AECLKOUT1 See -33and Figure AAOE/ASOE a AAWE/ASWE a AR/W Aardy B Deasserted Setup = Hold =ACEx ABE70 ABA10 AED630 Read Data Aeclkout Aardya Asserted Deasserted Strobe Setup = Extended StrobeABA10 AED630 Setup time, read AEDx valid before Aeclkout high ASADS/ASRE B AAOE/ASOE B AAWE/ASWEB SM320C6455-EPBE1 BE2 BE3 BE4 EA1 EA2 EA3 EA4 Write Latency = Hold Holda HOLD/HOLDA TimingHHOLDAL-HOLDL Hold time, Hold low after Holda low DSP Owns Bus Busreq Timing Delay time, Aeclkout high to Abusreq valid AECLKOUTx 11.1 I2C Device-Specific Information 11 I2C Peripheral I2CEMDR I2COARI2CCLKH I2CSAR I2CXSR 51. I2C Registers 11.2 I2C Peripheral Register Descriptions 11.3 I2C Electrical Data/Timing Standard Mode Fast Mode MIN MAX Start Stop SDA SCLStop Start Stop Start Repeated 43. I2C Transmit Timings 54. HPI Control Registers Host-Port Interface HPI PeripheralHPI Device-Specific Information HPI Peripheral Register Descriptions HPI Electrical Data/Timing NO.PARAMETER See -56through Figure HD150 HCS HasHCNTL10 HR/W Hhwil Hstrobea Hrdyb HR/W Hhwil Hstrobe a 46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used 48. HPI32 Read Timing has Not Used, Tied High 49. HPI32 Read Timing has Used Input HCS input Has input HCNTL10 Input HR/W input Input HCS input HD310 input 51. HPI32 Write Timing has Used Multichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers 720 850 1000/-1000 McBSP Electrical Data/Timing FIXED-POINT Digital Signal Processor Clks Clks ClkrClkx Bit Bitn-1 Master Slave MIN MAXMASTER3 Slave MIN MAX Clkx FSX Hold time, DR valid after Clkx high + 36P Setup time, DR valid before Clkx high 18PMaster Slave MIN 198 199 Ethernet Bus Ethernet MAC Emac Interface Modes Emac Device-Specific Information Rmii 70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii ModesBall Number Device PIN Name Interface Mode Clocking 71. Ethernet MAC Emac Control Registers Emac Peripheral Register Descriptions RX7FREEBUFFER MacconfigSoftreset RX6FREEBUFFER HEX Address Range Acronym 72. Emac Statistics Registers 02C8 2000 02C8 3FFF Emac Descriptor Memory 73. Emac Control Module Registers74. Emac Descriptor Memory Mtclk Emac Electrical Data/TimingMbps Gmii Only Mrclk Input MRXD3−MRXD0 GmtclkOutput Mrclk Input MRXD7−MRXD4GMII only Gmtclk Output Mtclk Input MTXD7−MTXD4GMII onlyMTXD3−MTXD0 Mtxen Outputs Rmrefclk Input Emac Rmii Electrical Data/Timing Mrxer Inputs 720 1000/-1000 Unit MRXD1-MRXD0 Mcrsdv Emac Rgmii Electrical Data/Timing Cycle time, TXC Mbps 40*t cTXC 60*t cTXC 70. Emac Transmit Interface Timing Rgmii OperationAB Mdio Peripheral Register Descriptions 89. Mdio Registers Management Data Input/Output MdioMdio Device-Specific Information Mdio output Delay time, Mdclk low to Mdio data output valid 100Mdclk Mdio input 92. Timer 0 Registers TimersTimers Device-Specific Information Timers Peripheral Register Descriptions TINPLx TOUTLx Timers Electrical Data/Timing94. Timing Requirements for Timer Inputs1 see Figure 96. VCP2 Registers Enhanced Viterbi-Decoder Coprocessor VCP216.1 VCP2 Device-Specific Information 16.2 VCP2 Peripheral Register Descriptions Tbsd Enhanced Turbo Decoder Coprocessor TCP217.1 TCP2 Device-Specific Information Tbhd 97. TCP2 Registers 17.2 TCP2 Peripheral Register Descriptions PCI Device-Specific Information 98. Default Values for PCI Configuration RegistersRegister Default Value Peripheral Component Interconnect PCI PCI Peripheral Register Descriptions 99. PCI Configuration Registers 100. PCI Back End Configuration Registers 101. DSP-toPCI Address Translation Registers HEX Address Offset Acronym Register Name 102. PCI Hook Configuration Registers103. PCI External Memory Space 4AFF Ffff 48FF Ffff49FF Ffff 4A7F Ffff PCI Electrical Data/Timing 105. Utopia Data Queues Receive and Transmit Registers Utopia Device-Specific InformationUtopia Peripheral Register Descriptions 104. Utopia Registers Urclk Utopia Electrical Data/Timing106. Timing Requirements for UXCLK1 see Figure Uxclk Uxclav Uxenb Uxsoc Uxclk UXDATA70UXADDR40 P48 0x1F Urclk URDATA70 URADDR40 N Urclav Urenb Ursoc 112. RapidIO Control Registers Serial RapidIO Srio PortSerial RapidIO Device-Specific Information Serial RapidIO Peripheral Register Descriptions RIOBLK3ENSTAT RIOBLK2ENRIOBLK2ENSTAT RIOBLK3EN RIODOORBELL3ICCR RIODOORBELL2ICSRRIODOORBELL2ICCR RIODOORBELL3ICSR RIOINTDST0DECODE RioerrrstevnticrrRIOERRRSTEVNTICRR2 RIOERRRSTEVNTICRR3 RIOLSU4REG3 RIOLSU4REG0RIOLSU4REG1 RIOLSU4REG2 RIOQUEUE7RXDMAHDP RIOQUEUE4RXDMAHDPRIOQUEUE5RXDMAHDP RIOQUEUE6RXDMAHDP RIORXUMAPH1 RIORXUMAPL0RIORXUMAPH0 RIORXUMAPL1 RapidIO Peripheral-Specific Registers Riohostbaseidlock RiolclcfghbarRiolclcfgbar Riobaseid RIOSP0RATEEN RioctrlcaptRiopwtgtid RIOSP0ERRDET Serial RapidIO Electrical Data/Timing 245 113. Gpio Registers General-Purpose Input/Output GpioGpio Device-Specific Information Gpio Peripheral Register Descriptions Pulse duration, GPOx low 36P 8 Gpio Electrical Data/Timing114. Timing Requirements for Gpio Inputs12 see Figure Pulse duration, GPOx high 36P 8 Trace Emulation Features and CapabilityAdvanced Event Triggering AET 116. Timing Requirements for Jtag Test Port see Figure Delay time, TCK low to TDO validIeee 1149.1 Jtag Jtag Device-Specific Information Added 0.83 ns C6455-1200 1.2-GHz CPU Cycle Time Revision HistoryC6455 Revision History See ADDITIONS/MODIFICATIONS/DELETIONS AIR Flow Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZThermal Data Packaging Information Qty Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Page Rfid Products ApplicationsDSP