Texas Instruments SM320C6455-EP manual 1 PLL1 Controller Device-Specific Information

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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR

+1.8 V

EMI Filter

C1 C2

560 pF 0.1 mF

				SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
TMS320C6455 DSP
PLLV1
						PLL1 Controller
	PLLREF	PLL1	PLLOUT
				PLLEN (PLLCTL.[0])
CLKIN1 (B)	DIVIDER PREDIV			SYSREFCLK
				(C64x+ MegaModule)
	/1, /2, /3	PLLM
				DIVIDER D2(A)
		x1, x15,	1
	ENA	x20, x25,
		x30, x32	0	/3		SYSCLK2
	PREDEN (PREDIV.[15])			DIVIDER D3(A)
				/6		SYSCLK3
				DIVIDER D4
				/2, /4,		SYSCLK4
				..., /16
						(Internal EMIF Clock Input)
		D4EN (PLLDIV4.[15])		ENA
				DIVIDER D5
				/1, /2,		SYSCLK5
				..., /8
		D5EN (PLLDIV5.[15])		ENA		(Emulation and Trace)
AECLKIN (External EMIF Clock Input)
			/1, /2,					GP0
			..., /8
			CLKDIV
			(CTRL.[18:16])		0 1	AECLKINSEL	1 0	SYSCLKOUT_EN
						(AEA[15] pin)		(AEA[4] pin)
			(EMIF Input Clock)		EMIFA
				AECLKOUT		GP1/SYSCLK4

A.DIVIDER D2 and DIVIDER D3 are always enabled.

B.CLKIN1 is a 3.3-V signal.

Figure 7-10. PLL1 and PLL1 Controller

7.7.1PLL1 Controller Device-Specific Information

7.7.1.1Internal Clocks and Maximum Operating Frequencies

As shown in Figure 7-10, the PLL1 controller generates several internal clocks including the system reference clock (SYSREFCLK), and the system clocks (SYSCLK2/3/4/5). The high-frequency clock signal SYSREFCLK is directly used to clock the C64x+ megamodule (including the CPU) and also serves as a reference clock for the rest of the DSP system.

Dividers D2, D3, D4, and D5 divide the high-frequency clock SYSREFCLK to generate SYSCLK2, SYSCLK3, SYSCLK4, and SYSCLK5, respectively. The system clocks are used to clock different portions of the DSP:

∙SYSCLK2 is used to clock the switched central resources (SCRs), EDMA3, VCP2, TCP2, and RapidIO, as well as the data bus interfaces of the EMIFA and DDR2 Memory Controller.

∙SYSCLK3 clocks the PCI, HPI, UTOPIA, McBSP, GPIO, TIMER, and I2C peripherals, as well as the configuration bus of the PLL2 Controller.

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