Texas Instruments SM320C6455-EP manual Write Latency =

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

Write

Latency =

1(B)

AECLKOUT
	1				1
ACEx
	2				3
ABE[7:0]	BE1	BE2	BE3	BE4
	4				5
AEA[19:0]/ABA[1:0]	EA1	EA2	EA3	EA4
	10	10			11
AED[63:0]		Q1	Q2	Q3	Q4
ASADS/ASRE (B)	8				8
AAOE/ASOE (B)
	12				12
AAWE/ASWE(B)

AThe following parameters are programmable via the EMIFA Chip Select n Configuration Register (CESECn):

−Read latency (R_L TNCY): 1-, 2-, or 3-cycle read latency

−W rite latency (W_LTNCY): 0-, 1-, 2-, or 3-cycle write latency

−ACEx assertion length (CE_EXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued (CE_EXT = 0). For synchronous FIFO interface, ACEx is active when ASOE is active (CE_EXT = 1).

−Function of ASADS/ASRE (R_ENABLE): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles (R_ENABLE = 0). For FIFO interface, ASADS/ASRE acts as SRE with NO deselect cycles (R_ENABLE = 1).

−In this figure W_L TNCY = 1, CE_EXT = 0, R_ENABLE = 0, and SSEL = 1.

BAAOE/ASOE, and AAWE/ASWE operate as ASOE, and ASWE, respectively, during programmable synchronous interface accesses.

Figure 7-38. Programmable Synchronous Interface Write Timing for EMIFA (With Write Latency = 1) (A)

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