Texas Instruments SM320C6455-EP manual Signal Name

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

Table 2-3. Terminal Functions (continued)

SIGNAL

NAME

RESET

NMI

NO.	TYPE(1)	IPD/IPU(2)	DESCRIPTION
	RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
AG14	I		Device reset
			Nonmaskable interrupt, edge-driven (rising edge)
AH4	I	IPD	Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin
			is not used, it is recommended that the NMI pin be grounded versus relying on

the IPD.

RESETSTAT

POR

GP[7]

GP[6]

GP[5]

GP[4]

URADDR3/PREQ/

GP[15]

URADDR2/PINTA(5)/ GP[14]

URADDR1/PRST/

GP[13]

URADDR0/PGNT/

GP[12]

FSX1/GP[11]

FSR1/GP[10]

DX1/GP[9]

DR1/GP[8]

CLKX1/GP[3]

URADDR4/PCBE0/

GP[2]

SYSCLK4/GP[1]

CLKR1/GP[0]

AE14	O
AF14	I
AG2	I/O/Z	IPD
AG3	I/O/Z	IPD
AJ2	I/O/Z	IPD
AH2	I/O/Z	IPD
P2	I/O/Z
P3	I/O/Z
R5	I/O/Z
R4	I/O/Z
AG4	I/O/Z	IPD
AE5	I/O/Z	IPD
AG5	I/O/Z	IPD
AH5	I/O/Z	IPD
AF5	I/O/Z	IPD
P1	I/O/Z
AJ13	O/Z	IPD
AF4	I/O/Z	IPD

Reset Status pin. The RESETSTAT pin indicates when the device is in reset Power on reset.

General-purpose input/output (GPIO) pins (I/O/Z).

UTOPIA received address pins or PCI peripheral pins or General-purpose input/output (GPIO) [15:12, 2] pins (I/O/Z) [default]

PCI bus request (O/Z) or GP[15] (I/O/Z) [default] PCI interrupt A (O/Z) or GP[14] (I/O/Z) [default] PCI reset (I) or GP[13] (I/O/Z) [default]

PCI bus grant (I) or GP[12] (I/O/Z) [default]

PCI command/byte enable 0 (I/O/Z) or GP[2] (I/O/Z) [default]

McBSP1 transmit clock (I/O/Z) or GP[3] (I/O/Z) [default]

McBSP1 receive clock (I/O/Z) or GP[0] (I/O/Z) [default]

GP[1] pin (I/O/Z). SYSCLK4 is the clock output at 1/8 of the device speed (O/Z) or this pin can be programmed as a GP[1] pin (I/O/Z) [default].

HOST-PORT INTERFACE (HPI) or PERIPHERAL COMPONENT INTERCONNECT (PCI)

				PCI enable pin. This pin controls the selection (enable/disable) of the HPI and
PCI_EN	Y29	I	IPD	GP[15:8], or PCI peripherals. This pin works in conjunction with the
				MCBSP1_EN (AEA5 pin) to enable/disable other peripherals (for more details,
				see Section 3, Device Configuration).
HINT/PFRAME	U3	I/O/Z		Host interrupt from DSP to host (O/Z) or PCI frame (I/O/Z)
HCNTL1/PDEVSEL	U4	I/O/Z		Host control - selects between control, address, or data registers (I) [default] or
				PCI device select (I/O/Z)
HCNTL0/PSTOP	U5	I/O/Z		Host control - selects between control, address, or data registers (I) [default] or
				PCI stop (I/O/Z)
				Host half-word select - first or second half-word (not necessarily high or low
HHWIL/PCLK	V3	I/O/Z		order)
				[For HPI16 bus width selection only] (I) [default] or PCI clock (I)
HR/W/PCBE2	T5	I/O/Z		Host read or write select (I) [default] or PCI command/byte enable 2 (I/O/Z)
HAS/PPAR	T3	I/O/Z		Host address strobe (I) [default] or PCI parity (I/O/Z)
HCS/PPERR	U6	I/O/Z		Host chip select (I) [default] or PCI parity error (I/O/Z)
HDS1/PSERR(5)	U2	I/O/Z		Host data strobe 1 (I) [default] or PCI system error (I/O/Z)
HDS2/PCBE1	U1	I/O/Z		Host data strobe 2 (I) [default] or PCI command/byte enable 1 (I/O/Z)
HRDY/PIRDY	T4	I/O/Z		Host ready from DSP to host (O/Z) [default] or PCI initiator ready (I/O/Z)
URADDR3/PREQ/	P2	I/O/Z		UTOPIA received address pin 3 (URADDR3) (I) or PCI bus request (O/Z) or
GP[15]				GP[15] (I/O/Z) [default]

(5)These pins function as open-drain outputs when configured as PCI pins.

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