Texas Instruments SM320C6455-EP manual Enhanced Viterbi-Decoder Coprocessor VCP2, VCP2 Registers

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2)

7.16.1 VCP2 Device-Specific Information

The C6455 device has a high-performance embedded coprocessor [Viterbi-Decoder Coprocessor (VCP2) that significantly speeds up channel-decoding operations on-chip. The VCP2 operating at CPU clock divided-by-4 can decode over 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and flexible polynomials, while generating hard decisions or soft decisions. Communications between the VCP2 and the CPU are carried out through the EDMA3 controller.

The VCP2 supports:

∙Unlimited frame sizes

∙Code rates 3/4, 1/2, 1/3, 1/4, and 1/5

∙Constraint lengths 5, 6, 7, 8, and 9

∙Programmable encoder polynomials

∙Programmable reliability and convergence lengths

∙Hard and soft decoded decisions

∙Tail and convergent modes

∙Yamamoto logic

∙Tail biting logic

∙Various input and output FIFO lengths

For more detailed information on the VCP2, see the TMS320C645x DSP Viterbi-Decoder Coprocessor 2 (VCP2) Reference Guide (literature number SPRU972).

7.16.2 VCP2 Peripheral Register Description(s)

Table 7-96. VCP2 Registers

	EDMA BUS	CONFIGURATION BUS	ACRONYM	REGISTER NAME
HEX ADDRESS RANGE		HEX ADDRESS RANGE
	5800 0000	-	VCPIC0	VCP2 Input Configuration Register 0
	5800 0004	-	VCPIC1	VCP2 Input Configuration Register 1
	5800 0008	-	VCPIC2	VCP2 Input Configuration Register 2
	5800 000C	-	VCPIC3	VCP2 Input Configuration Register 3
	5800 0010	-	VCPIC4	VCP2 Input Configuration Register 4
	5800 0014	-	VCPIC5	VCP2 Input Configuration Register 5
	5800 0018 - 5800 0044		-	Reserved
	5800 0048	-	VCPOUT0	VCP2 Output Register 0
	5800 004C	-	VCPOUT1	VCP2 Output Register 1
	5800 0050 - 5800 007C		-	Reserved
	5800 0080	N/A	VCPWBM	VCP2 Branch Metrics Write FIFO Register
	5800 0084 - 5800 009C		-	Reserved
	5800 00C0	N/A	VCPRDECS	VCP2 Decisions Read FIFO Register
	N/A	02B8 0018	VCPEXE	VCP2 Execution Register
	N/A	02B8 0020	VCPEND	VCP2 Endian Mode Register
	N/A	02B8 0040	VCPSTAT0	VCP2 Status Register 0
	N/A	02B8 0044	VCPSTAT1	VCP2 Status Register 1
	N/A	02B8 0050	VCPERR	VCP2 Error Register
			-	Reserved
	N/A	02B8 0060	VCPEMU	VCP2 Emulation Control Register
	N/A	02B8 0064 - 02B9 FFFF	-	Reserved
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