Texas Instruments SM320C6455-EP manual HOLD/HOLDA Timing, DSP Owns Bus, Hold Holda, DSP Aeclkout

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.10.4 HOLD/HOLDA Timing

Table 7-48. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module(1) (see Figure 7-39)

		-720
		-850
NO.		A-1000/-1000		UNIT
		-1200
		MIN	MAX
3	th(HOLDAL-HOLDL)Hold time, HOLD low after HOLDA low	E		ns

(1)E = the EMIF input clock (ECLKIN) period in ns for EMIFA.

Table 7-49. Switching Characteristics Over Recommended Operating Conditions for the HOLD/HOLDA

Cycles for EMIFA Module(1)(2) (see Figure 7-39)

			-720
			-850
NO.		PARAMETER	A-1000/-1000		UNIT
			-1200
			MIN	MAX
1	td(HOLDL-EMHZ)	Delay time, HOLD low to EMIFA Bus high impedance	2E	(3)	ns
2	td(EMHZ-HOLDAL)	Delay time, EMIF Bus high impedance to HOLDA low	0	2E	ns
4	td(HOLDH-EMLZ)	Delay time, HOLD high to EMIF Bus low impedance	2E	7E	ns
5	td(EMLZ-HOLDAH)	Delay time, EMIFA Bus low impedance to HOLDA high	0	2E	ns

(1)E = the EMIF input clock (ECLKIN) period in ns for EMIFA.

(2)EMIFA Bus consists of: ACE[5:2], ABE[7:0], AED[63:0], AEA[19:0], ABA[1:0], AR/W, ASADS/ASRE, AAOE/ASOE, and AAWE/ASWE.

(3)All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay time can be achieved.

	DSP Owns Bus	External Requestor	DSP Owns Bus
		Owns Bus
		3
HOLD
	2		5
HOLDA
EMIF Bus (A)	1		4
	DSP		DSP

AECLKOUT

A.EMIFA Bus consists of: ACE[5:2], ABE[7:0], AED[63:0], AEA[19:0], ABA[1:0], AR/W, ASADS/ASRE, AAOE/ASOE, and AAWE/ASWE.

Figure 7-39. HOLD/HOLDA Timing for EMIFA

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