Texas Instruments SM320C6455-EP manual See -56through Figure, No.Parameter

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

Table 7-56. Switching Characteristics for Host-Port Interface Cycles(1)(2)

(see Table 7-56through Figure 7-51)

NO.PARAMETER

-720 -850

A-1000/-1000 UNIT -1200

1td(HSTBL-HDV)

Delay time, HSTROBE low to DSP data valid

Case 1. HPIC or HPIA read

Case 2. HPID read with no auto-increment(3)

Case 3. HPID read with auto-increment and read FIFO initially empty(3)

Case 4. HPID read with auto-increment and data previously prefetched into the read FIFO

MIN	MAX
5	15
	9 * M + 20
	9 * M + 20 ns
5	15

2tdis(HSTBH-HDV)

3ten(HSTBL-HD)

4td(HSTBL-HRDYH)

5td(HSTBH-HRDYH)

6td(HSTBL-HRDYL)

7td(HDV-HRDYL)

34td(DSH-HRDYL)

35td(HSTBL-HRDYL)

36td(HASL-HRDYH)

Disable time, HD high-impedance from HSTROBE high

Enable time, HD driven from HSTROBE low

Delay time, HSTROBE low to HRDY high

Delay time, HSTROBE high to HRDY high

	Case 1.	HPID read with no
Delay time, HSTROBE low to	auto-increment(3)
HRDY low	Case 2.	HPID read with auto-increment
	and read FIFO initially empty(3)

Delay time, HD valid to HRDY low

Case 1. HPIA write(3)

Delay time, HSTROBE high to

HRDY lowCase 2. HPID write with no auto-increment(3)

Delay time, HSTROBE low to HRDY low for HPIA write and FIFO not empty(3)

Delay time, HAS low to HRDY high

1	4	ns
3	15	ns
	12	ns
	12	ns
10	* M + 20
		ns
10	* M + 20
0		ns
5	* M + 20
5	* M + 20	ns
40	* M + 20	ns
	12	ns

(1)M = SYSCLK3 period = 6/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use M = 6 ns.

(2)HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

(3)Assumes the HPI is accessing L2/L1 memory and no other master is accessing the same memory location.

Submit Documentation Feedback C64x+ Peripheral Information and Electrical Specifications 181