Texas Instruments SM320C6455-EP XINT0, RINT1, XINT1, TINTLO0, TINTHI0, TINTLO1, TINTHI1, Interr

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com

SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

Table 7-10. C6455 System Event Mapping (continued)

EVENT NUMBER	INTERRUPT EVENT	DESCRIPTION
41	XINT0	McBSP0 transmit interrupt
42	RINT1	McBSP1 receive interrupt
43	XINT1	McBSP1 transmit interrupt
44 - 50	Reserved	Reserved. Do not use.
51	GPINT0	GPIO interrupt
52	GPINT1	GPIO interrupt
53	GPINT2	GPIO interrupt
54	GPINT3	GPIO interrupt
55	GPINT4	GPIO interrupt
56	GPINT5	GPIO interrupt
57	GPINT6	GPIO interrupt
58	GPINT7	GPIO interrupt
59	GPINT8	GPIO interrupt
60	GPINT9	GPIO interrupt
61	GPINT10	GPIO interrupt
62	GPINT11	GPIO interrupt
63	GPINT12	GPIO interrupt
64	GPINT13	GPIO interrupt
65	GPINT14	GPIO interrupt
66	GPINT15	GPIO interrupt
67	TINTLO0	Timer 0 lower counter interrupt
68	TINTHI0	Timer 0 higher counter interrupt
69	TINTLO1	Timer 1 lower counter interrupt
70	TINTHI1	Timer 1 higher counter interrupt
71	EDMA3CC_INT0	EDMA3CC completion interrupt - Mask0
72	EDMA3CC_INT1	EDMA3CC completion interrupt - Mask1
73	EDMA3CC_INT2	EDMA3CC completion interrupt - Mask2
74	EDMA3CC_INT3	EDMA3CC completion interrupt - Mask3
75	EDMA3CC_INT4	EDMA3CC completion interrupt - Mask4
76	EDMA3CC_INT5	EDMA3CC completion interrupt - Mask5
77	EDMA3CC_INT6	EDMA3CC completion interrupt - Mask6
78	EDMA3CC_INT7	EDMA3CC completion interrupt - Mask7
79	EDMA3CC_ERRINT	EDMA3CC error interrupt
80	Reserved	Reserved. This system event is not connected and, therefore, not
		used.
81	EDMA3TC0_ERRINT	EDMA3TC0 error interrupt
82	EDMA3TC1_ERRINT	EDMA3TC1 error interrupt
83	EDMA3TC2_ERRINT	EDMA3TC2 error interrupt
84	EDMA3TC3_ERRINT	EDMA3TC3 error interrupt
85 - 95	Reserved	Reserved. These system events are not connected and, therefore,
		not used.
96(1)	INTERR	Interrupt Controller dropped CPU interrupt event
97(1)	EMC_IDMAERR	EMC invalid IDMA parameters
98 - 99	Reserved	Reserved. These system events are not connected and, therefore,
		not used.
100(1)	EFIINTA	EFI interrupt from side A
101(1)	EFIINTB	EFI interrupt from side B
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