Texas Instruments SM320C6455-EP manual FIXED-POINT Digital Signal Processor

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

software such as Code Composer Studio.

For the PCI host boot, the CPU is out of reset, but it executes an IDLE instruction until a DSP interrupt is generated by the host. The host can generate a DSP interrupt through the PCI peripheral by setting the DSPINT bit in the Back-End Application Interrupt Enable Set Register (PCIBINTSET) and the Status Set Register (PCISTATSET).

Note that the HPI host boot is a hardware boot mode while the PCI host boot is a software boot mode.

If PCI boot is selected, the on-chip bootloader configures the PLL1 Controller such that CLKIN1 is multiplied by 15. More specifically, PLLM is set to 0Eh (x15) and RATIO is set to 0 (÷1) in the PLL1 Multiplier Control Register (PLLM) and PLL1 Pre-Divider Register (PREDIV), respectively. The CLKIN1 frequency must not be greater than 50 MHz so that the maximum speed of the internal ROM, 750 MHz, is not violated. The CFGGP[2:0] pins must be set to 000b during reset for proper operation of the PCI boot mode.

As mentioned previously, a DSP interrupt must be generated at the end of the host boot process to begin execution of the loaded application. Because the DSP interrupt generated by the HPI and PCI is mapped to the EDMA event DSP_EVT (DMA channel 0), it will get recorded in bit 0 of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0.

∙EMIFA 8 bit ROM boot (BOOTMODE[3:0] = 0100b)

After reset, the device will begin executing software out of an Asynchronous 8 bit ROM located in EMIFA CE3 space using the default settings in the EMIFA registers. This boot mode is a hardware boot mode.

∙Master I2C boot (BOOTMODE[3:0] = 0101b)

After reset, the DSP can act as a master to the I2C bus and copy data from an I2C EEPROM or a device acting as an I2C slave to the DSP using a predefined boot table format. The destination address and length are contained within the boot table. This boot mode is a software boot mode.

∙Slave I2C boot (BOOTMODE[3:0] = 0110b)

A Slave I2C boot is also implemented, which programs the DSP as an I2C Slave and simply waits for a Master to send data using a standard boot table format.

Using the Slave I2C boot, a single DSP or a device acting as an I2C Master can simultaneously boot multiple slave DSPs connected to the same I2C bus. Note that the Master DSP may require booting via an I2C EEPROM before acting as a Master and booting other DSPs.

The Slave I2C boot is a software boot mode.

∙Serial RapidIO boot (BOOTMODE[3:0] = 1000b through 1111b) After reset, the following sequence of events occur:

–The on-chip bootloader configures device registers, including SerDes, and EDMA3

–The on-chip bootloader resets the peripheral's state machines and registers

–RapidIO ports send idle control symbols to initialize SerDes ports

–The host explores the system with RapidIO maintenance packets

–The host identifies, enumerates, and initializes the RapidIO device

–The host controller configures DSP peripherals through maintenance packets

–The application software is sent from the host controller to DSP memory

–The DSP CPU is awakened by interrupt such as a RapidIO DOORBELL packet

–The application software is executed and normal operation follows

For Serial RapidIO boot, BOOTMODE2 (L26 pin) is used in conjunction with CFGGP[2:0] (T26, U26, and U25 pins, respectively) to determine the device address within the RapidIO network. BOOTMODE2 is the MSB of the address, while CFGGP[2:0] are used as the three LSBs–giving the user the opportunity to have up to 16 unique device IDs.

BOOTMODE[1:0] (L25 and P26, respectively) denote the configuration of the RapidIO peripheral; i.e., "00b" refers to RapidIO Configuration 0. For exact device RapidIO Configurations, see the TMS320C645xx Bootloader User's Guide (literature number SPRUEC6).

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