Texas Instruments SM320C6455-EP manual McBSP Device-Specific Information

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.13.1 McBSP Device-Specific Information

The CLKS signal is shared by both McBSP0 and McBSP1 on this device. Also, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater.

The McBSP Data Receive Register (DRR) and Data Transmit Register (DXR) can be accessed through two separate busses: a configuration bus and a data bus. Both paths can be used by the CPU and the EDMA. The data bus should be used to service the McBSP as this path provides better performance. However, since the data path shares a bridge with the PCI and UTOPIA peripherals (see Figure 4-1), the configuration path should be used in cases where these peripherals are being used to avoid any performance degradation. Note that the PCI peripheral consists of an independent master and slave. Performance degradation is only a concern when this peripheral is used to initiate transactions on the external bus.

7.13.1.1 McBSP Peripheral Register Description(s)

Table 7-57. McBSP 0 Registers

HEX ADDRESS RANGE	ACRONYM	REGISTER NAME
028C 0000	DRR0	McBSP0 Data Receive Register via Configuration Bus
3000 0000	DRR0	McBSP0 Data Receive Register via EDMA3 Bus
028C 0004	DXR0	McBSP0 Data Transmit Register via Configuration Bus
3000 0010	DXR0	McBSP0 Data Transmit Register via EDMA Bus
028C 0008	SPCR0	McBSP0 Serial Port Control Register
028C 000C	RCR0	McBSP0 Receive Control Register
028C 0010	XCR0	McBSP0 Transmit Control Register
028C 0014	SRGR0	McBSP0 Sample Rate Generator register
028C 0018	MCR0	McBSP0 Multichannel Control Register
028C 001C	RCERE00	McBSP0 Enhanced Receive Channel Enable
		Register 0 Partition A/B
028C 0020	XCERE00	McBSP0 Enhanced Transmit Channel Enable
		Register 0 Partition A/B
028C 0024	PCR0	McBSP0 Pin Control Register
028C 0028	RCERE10	McBSP0 Enhanced Receive Channel Enable
		Register 1 Partition C/D
028C 002C	XCERE10	McBSP0 Enhanced Transmit Channel Enable
		Register 1 Partition C/D
028C 0030	RCERE20	McBSP0 Enhanced Receive Channel Enable
		Register 2 Partition E/F
028C 0034	XCERE20	McBSP0 Enhanced Transmit Channel Enable
		Register 2 Partition E/F
028C 0038	RCERE30	McBSP0 Enhanced Receive Channel Enable
		Register 3 Partition G/H
028C 003C	XCERE30	McBSP0 Enhanced Transmit Channel Enable
		Register 3 Partition G/H
028C 0040 - 028F FFFF	-	Reserved

COMMENTS

The CPU and EDMA3 controller can only read this register; they cannot write to it.

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